It is generally assumed that achieving a narrow distribution of physical gate length (Lpoly) for the poly conductor layer
helps improve power performance metrics of modern integrated circuits. However, in advanced 90 nm technologies,
there are other drivers of chip performance. In this paper we show that a global optimization of all variables is necessary
to achieve the optimum performance at the lowest leakage. We will also describe how systematic physical gate-length
variation can improve core matching in multicore designs.
The implementation of alternating phase shifted mask lithography for the poly-conductor level of IBM's leading edge 65nm microprocessor is described. Very broad and 'resolution-enhancement-technology generic' design rules, referred to as radical design restrictions, are demonstrated to be key enablers of alternating phase shifted mask design. The benefit of these radical design restrictions over conventional design rules and other alternating phase shifted mask design approaches is detailed for key aspects of the design flow.
The use of alternating phase shifting masks (alt-PSM) can significantly improve lithographic process windows. However, the existence of phase error between the nominal 0 and 180 degree phase regions can cause printed lines to shift laterally toward each other in pairs at image planes away from the best focus. Such asymmetry, especially evident with small ground rules, challenges both overlay and critical dimension (CD) control. To minimize such effect, tight control in phase angle has been implemented, which contributes to the higher fabrication cost for an alt-PSM. Since the effect of the phase error varies with different lithographic conditions, knowing how much phase control is necessary for a given lithographic situation becomes essential to the reduction of the mask fabrication cost. Although this phenomenon has been studied in the past with a number of simulations and experiments, a systematic understanding of its mechanism, especially its interaction with CD and numerical aperture has not been reported. This paper explores the theoretical relationship between phase error and important parameters of photolithographic processes, such as CD, numerical apertures (NA), and overlay tolerance. A simple equation of the phase error is developed, which indicates that the effect of the phase error is inversely proportional to both phase error and defocus. We have compared the predictions of this theory to our first experimental results from a test mask and a good agreement is found. Based on this theory, we develop the quantity “tolerable phase error” relating the effect of the phase error to the CD, pitch, and depth of focus of the imaging system. We have found that for a system with depth of focus of +/- 300 nm, a phase error control about 2 degrees is necessary to realize a line shift control of less than 2.5% of the CD for the most aggressive feature size at any NA. We also note that the control of phase error can be relaxed at high NA. Calculations for 193 nm as well as 157 nm lithography are presented.
New degrees of freedom can be optimized in mask shapes
when the source is also adjustable, because required image symmetries can be provided by the source rather than the collected wave front. The optimized mask will often consist of novel sets of shapes that are quite different in layout from the target integrated circuit patterns. This implies that the optimization algorithm should have good global convergence
properties, since the target patterns may not be a suitable starting solution. We have developed an algorithm that can optimize mask and source without using a starting design. Examples are shown where the
process window obtained is between two and six times larger than that achieved with standard reticle enhancement techniques (RET). The optimized
masks require phase shift, but no trim mask is used. Thus far we can only optimize two-dimensional patterns over small fields (periodicities
of ;1 mm or less), though patterns in two separate fields can be jointly optimized for maximum common window under a single source. We also discuss mask optimization with fixed source, source optimization
with fixed mask, and the retargeting of designs in different mask regions to provide a common exposure level.
Continuous downward pressure on chip size has led to aggressive ground rule shrink paths in the semiconductor industry, especially in the DRAM sector. Ever-decreasing feature sizes have necessitated the extensive use of attenuated phase shift masks, off-axis illumination, optical proximity correction, etc. For the foreseeable future, the ability to meet the demands of the design is closely tied to the extendibility of ArF lithography. This paper explores DRAM lithographic scaling by predicting required process latitude and depth of focus based on litho-graphic merit function scaling. This allows the predictions to be anchored against data collected on current products, as well as indicating the rate at which learning must occur for a ground rule shrink to be successful. Modeling of ArF extendibility is presented, with particular emphasis on the role of alternating phase shift masks. Additionally, simple signal-to-noise argu-ments are made in connection with the required process window for a given technology, taking into the account fundamental error sources of the process. The analyses are anchored to existing technologies wherever possible. The results indicate that ArF lithography will extend through the 90 nm technology node with a critical dependence on alternating phase shift masks.
Silicon-containing bilayer thin-film imaging resists versus single layer resists for a variety of different mask types, from both a focus-expose window, etch selectivity, and process integration perspective are examined. Comparable lithographic performance is found for 248 nm single layer and bilayer resists for several mask levels including: a 135 nm dense contact/deep trench mask level, a 150 and 125 nm equal line space mask printed over trench topography, and dual damascene mask levels with both vias and line levels. The bilayer scheme is shown to significantly relax the dielectric to resist etch selectivity constraint for the case of a dense contact or trench hardmask level, where high aspect ratio dielectric features are required. Only a bilayer resist scheme in combination with a transfer etch process enables the line/space pattern transfer from the imaging layer to the bottom of a trench with a combined aspect ratio > 10. When the single layer resist depth of focus window is limited by both the topography and variations in the underlying dielectric stack thickness, as is the case for the dual damascene via and line levels, bilayer resist is shown to be a practical alternative.
New degrees of freedom can be optimized in mask shapes when the source is also adjustable, because required image symmetries can be provided by the source rather than the collected wavefront. The optimized mask will often consist of novel sets of shapes that are quite different in layout from the target IC patterns. This implies that the optimization algorithm should have good global convergence properties, since the target patterns may not be a suitable starting solution. We have developed an algorithm that can optimize mask and source without using a starting design. Examples are shown where the process window obtained is between 2 and 6 times larger than that achieved with standard RET methods. The optimized masks require phase shift, but no trim mask is used. Thus far we have only optimized 2D patterns over small fields (periodicities of approximately 1 micrometer or less). We also discuss mask optimization with fixed source, source optimization with fixed mask, and the re-targeting of designs in different mask regions to provide a common exposure level.
A double exposure technique, so called nano-stepping, was investigated to evaluate its benefit for very dense features to reduce line shortening, improve pattern fidelity and resolution capability. The technique involves relaxing the pitch of dense patterns in one dimension and filling in the missing patterns by exposing the same reticle again, offset by an appropriate amount. This method suffers only small throughput loss compared to conventional dual reticle exposure techniques. For 1D patterns, 100 nm lines and spaces can be printed with a 248 nm exposure tool and a half tone mask. Dense 2D contacts with various length to width ratios can be achieved with minimum distance to adjacent neighbors.
As product error budgets continue to shrink with decreasing ground rule, more attention is being paid to the effects of exposure tool lens aberrations. Interaction of the reticle pattern with the lens can cause both image placement shifts as well as variations of critical dimensions across the exposure field. A particularly subtle effect is the interaction of the reticle pattern orientation with lens aberrations. It can be shown that there is often a large difference in aberration-driven errors for patterns oriented differently relative to the lens axis. This paper develops the physical model behind this phenomenon as a function of pattern aspect ratio and orientation. Specific examines are given in reference to line width control and overlay for typical DRAM patterns, using both simulation and experimental dat. In addition, optimization schemes for pattern orientation are explored, as well as implications for practical implementation on exposure tools .We also show that pattern orientation can be optimized on a level-by- level basis to provide great benefit in CD and overlay error performance.
We combine lithographic simulation, experimental data and statistical modeling to build a predictive estimator of total device overlay. To generate accurate predictions of total overlay, we include error estimates on lens image placement, CD control, reticle and exposure tool alignment. Instead of combining these errors in ad hoc root sum square fashion to make overlay estimates, we construct a physical model of the device and metrology marker edge placement processes. The model comprehends the differential placement of metrology structures and device features due to lens and illumination system asymmetries and is therefore applicable to the evaluation of arbitrary illumination and pattern geometry conditions. Since we attempt to model the relative placement distribution of specific device features, the model produces overlay estimates that are directly relevant for device performance. The comparison of our total overlay estimate to device overlay sensitivity data allows a projection of the overlay related yield loss for a given device, process and tools et. Finally, our model allows the process engineer to made informative choices on the optimum error sources to pursue for improving overlay.