Dr. Se-Hyuk Im Profile

Dr. Se-Hyuk Im

at Canon Nanotechnologies, Inc

SPIE Involvement:

Author

Publications (3)

Proceedings Article | 23 March 2020 Paper

Addressing nanoimprint lithography mix and match overlay using drop pattern compensation

Mitsura Hiura, Satoshi Iino, Anshuman Cherala, Se-Hyuk Im, Mario Meissl, Logan Simpson, Ecron Thompson, Jin Choi

Proceedings Volume 11324, 113240C (2020) https://doi.org/10.1117/12.2552023

KEYWORDS: Distortion, Photomasks, Semiconducting wafers, Nanoimprint lithography, Optical alignment, Ultraviolet radiation, Overlay metrology, Wafer testing, Semiconductors

Read Abstract +

Imprint lithography is a promising technology for replication of nano-scale features. For semiconductor device applications, Canon deposits a low viscosity resist on a field by field basis using jetting technology. A patterned mask is lowered into the resist fluid, which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Overlay budgets play a large role in defining production readiness. As an example, DRAM devices require overlay on the order of 15-20% of the half pitch. Canon uses a through the mask (TTM) alignment system to measure a Moiré image anywhere in the field. This system can also record alignment errors of all fields and all marks. The data collected by the TTM system correlates very closely with an Archer measurement tool. In addition, a High Order Distortion Correction (HODC) system, which applies a heat input on a field by field basis through the use of a DMD array has been combined with magnification actuators to correct high order distortion terms up to K30. There is an additional distortion term that must also be addressed for the case of nanoimprint lithography. NIL drop patterns are typically designed to minimize resist fill time and create a uniform residual layer beneath the resist pattern. For device wafers, however, it is important to recognize that there are both long wavelength flatness errors coming from the wafer chuck and existing pattern topography from previously patterned levels that cause out of plane errors. When the mask comes in contact with the resist on the wafer, these out of plane errors can then induce mask bending, resulting in an additional distortion term. To minimize this distortion, a Drop Pattern Compensation (DPC) Model has been implemented to minimize the added distortion terms. In this paper we present an updated study and report on nanoimprint mix and match overlay improvements using DPC. In addition, we describe how the mode array and peak to valley thickness of the resist impacts distortion correction.

Proceedings Article | 26 September 2019 Presentation + Paper

Patterning, mask life, throughput and overlay improvements for high volume semiconductor manufacturing using nanoimprint lithography

Osamu Morimoto, Anshuman Cherala, Se-Hyuk Im, Mario Meissl, Yukio Takabayashi, Keita Sakai, Takehiko Iwanaga, Wei Zhang, Jin Choi

Proceedings Volume 11148, 111480M (2019) https://doi.org/10.1117/12.2535912

KEYWORDS: Photomasks, Optical lithography, Nanoimprint lithography, Stochastic processes, Semiconductor manufacturing, Particles, Semiconducting wafers, Lithography, Manufacturing equipment, Capillaries

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, we review progress on pattern capability, throughput, mask life and overlay. To minimize distortion and improve overlay, a Drop Pattern Compensation (DPC) method has been implemented to minimize the added overlay distortion terms. In this paper we describe the origins of the out of plane errors, and describe the method used to correct these errors along with some examples. Improvements to both cross matched machine overlay (XMMO) and imprint mix and match overlay (IMMO) are presented.

Proceedings Article | 16 May 2019 Paper

Topography and flatness induced overlay distortion correction using resist drop pattern compensation in nanoimprint lithography systems

Jin Choi, Anshuman Cherala, Mario Meissl, Mitsuru Hiura, Satoshi Iino, Se-Hyuk Im, Ahmed Hussein, Logan Simpson, Ryan Minter, Ecron Thompson

Proceedings Volume 10958, 109580C (2019) https://doi.org/10.1117/12.2515146

KEYWORDS: Photomasks, Semiconducting wafers, Distortion, Nanoimprint lithography, Overlay metrology, Optical alignment, Ultraviolet radiation, Data modeling, Semiconductors, Capillaries

Read Abstract +

Imprint lithography is a promising technology for replication of nano-scale features. For semiconductor device applications, Canon deposits a low viscosity resist on a field by field basis using jetting technology. A patterned mask is lowered into the resist fluid, which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Overlay budgets play a large role in defining production readiness. As an example, DRAM devices require overlay on the order of 20% of the half pitch. Canon uses a through the mask (TTM) alignment system to measure a Moiré image anywhere in the field. This system can also record alignment errors of all fields and all marks. The data collected by the TTM system correlates very closely with an Archer measurement tool. In addition, a High Order Distortion Correction (HODC) system, which applies a heat input on a field by field basis through the use of a DMD array has been combined with magnification actuators to correct high order distortion terms up to K30. There is an additional distortion term that must also be addressed for the case of nanoimprint lithography. NIL drop patterns are typically designed to minimize resist fill time and create a uniform residual layer beneath the resist pattern. For device wafers, however, it is important to recognize that there are both long wavelength flatness errors coming from the wafer chuck and existing pattern topography from previously patterned levels that cause out of plane errors. When the mask comes in contact with the resist on the wafer, these out of plane errors can then induce mask bending, resulting in an additional distortion term. To minimize this distortion, a Drop Pattern Compensation (DPC) Model has been implemented to minimize the added distortion terms. In this paper we describe the origins of the out of plane errors, and describe the model used to correct these errors along with some examples. Finally, results are presented for a device like wafer in which the overlay errors within a field are reduced from 5.4nm to 3.4nm, 3 sigma.

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