IBM Research recently announced that 2nm node Nanosheet Technology is able to deliver superior density, power and performance compared to today’s 7nm FinFET technology in mass production. To enable 2nm node Nanosheet Technology, advanced patterning solutions are required. Dimensional compression drives the need for advanced patterning solutions including wider use of extreme ultraviolet (EUV) lithography. This also creates higher in feature aspect ratios, which in turn creates additional challenges during plasma etch. As aspect ratios continue to increase, difficulty with in-feature ion, radical, and volatile species transport during plasma etch presents an exceptional challenge. Dimensional scaling and wider use of EUV increases the need for further reduction of critical dimension (CD) variability, including line edge and line width roughness. The introduction of 3-dimensional gate all around nanosheet architecture has introduced an additional unique set of patterning challenges to address for coming technology nodes. When combined with dimensional scaling there is a clear need for novel advanced patterning process solutions to enable future nodes. In this presentation a variety of these challenges and the impact they will have on device and node scaling will be introduced and reviewed.
Switching of phase change memory (PCM) materials between crystalline and amorphous phase with electrical pulses and optical properties make it an important candidate for storage class memory and neuromorphic computing. However, PCM materials can be sensitive to air exposure during integration, therefore in-vacuo RIE and encapsulation is important to provide the required oxygen diffusion barrier. Low temperature SiN deposition can be used for low thermal budget integration schemes provided a good film conformality is achieved and damage or etching to the PCM elements is mitigated. In this work, ammonia- (NH3-) free, plasma enhanced chemical vapor deposition (PECVD) SiN films deposited at 40°C (microwave plasma) and 200°C (inductively coupled plasma), are compared and wet etch rates and optical properties are evaluated. NH3-free SiN films were deposited using SiH4, N2, H2, and Ar as source gases. Tuning the plasma parameters during encapsulation we observed simultaneous selective etching of GST and controlled SiN film deposition. Hydrogen and argon addition to the plasma mixture provided the main control knob for in-situ GST trimming during deposition, avoiding any type of elemental or structural damage to the GST films.
Through‐silicon via etch (TSV) is critical to current and future advanced packaging schemes. For heterogeneous integration approaches in particular, where modular components are tightly packed together, these processes play an integral role. While etch processes for silicon appear well understood and the frontiers of plasma etch have led us to advanced cyclic processes for device fabrication such as atomic layer etching, TSV applications are fundamentally different due to their relative size and aspect ratio targets. Unlike small-scale etching, TSV feature etching has not shown exponential change over time. To achieve TSV targets such as high etch rate, high aspect ratio, and clean profiles to support filling, known solutions are employed such as cryogenic wafer temperatures, alternative hard mask schemes, and extremely short gas cycle times; these solutions require specialized equipment and/or a more complex integration scheme. We explore the creation of high-aspect ratio, diffusion-limited TSV etches with high PR selectivity (<50:1) and high aspect ratios while simultaneously aiming for a high etch rate all while using non-cryogenic temperatures and a standard photoresist mask. A focus on sidewall profile and sidewall damage is maintained.
Phase Change Memory (PCM) materials can be damaged during plasma exposure leading to changes in phase transition behavior. Etch-induced damage and crystallization properties of GeSbTe (GST) were evaluated as a function of substrate temperature, plasma chemistry, and plasma exposure time. Enhanced damage formation is related to selective elemental depletion and non-volatilized etch residue retention in the near surface region. These experiments validate literature findings that crystallization time increases with reduction in film thickness for GST samples capped with a thin SiO2 film, indicating the presence of a modified layer which serves as an interface layer material. A direct comparison of passivating properties of hydrofluorocarbon and hydrocarbon on GST can be more conclusive with a fine tuning of film thickness and an evaluation of total residue retention with depth profiling.
Analyses of unit process trace data are critical components of modern semiconductor manufacturing process control. While process development environments share many characteristics with manufacturing environments, development tools and processes may not be suitable candidates for the deployment of traditional trace analytics such as FDC applications. Here we describe the adaptive use of large scale, proactive process trace monitoring and reactive root cause analytics for supporting development operations. The large-scale monitoring application we have deployed is comprehensive in scope and scale and focusses on monitoring the stability of a chamber over time. The reactive root cause application we have deployed automatically searches large trace data spaces to identify trace data elements with potentially interesting relationships to variations in on-wafer measurements and is designed to handle the small sample sizes encountered frequently in development operations.
Plasma etch residue formation and its removal from silicon nitride (SiN) films deposited at 200ºC, 480ºC and 700ºC is explored. X-Ray Photoelectron Spectroscopy (XPS) measurements showed that SiN contains more nitrogen (N) and less oxygen (O) with increasing deposition temperature. SiN films were etched in an Inductively Coupled Plasma (ICP) reactor in a halogen/hydrofluorocarbon (H:HFC) gas mixture; the carbon (C) containing species in the resulting residue films were studied as a function of the H:HFC ratio in the plasma. Post-plasma etch cleaning methods of the SiN surface were compared, these included: wet treatment with diluted hydrofluoric acid (dHF), sputtering with argon (Ar) plasma, and combined dHF and Ar plasma. After etch, Secondary Ion Mass Spectroscopy (SIMS) and XPS data showed formation of fluorocarbon (FC) films on SiN. FC film thickness after etch was estimated from XPS to reach up to 2 nm. Ultimately the SiN etch rate was shown to drop with increasing deposited C thickness while the lower nitrogen content in the SiN film (i.e. 200ºC) led to higher etch rate, which is in good agreement with literature. Ar plasma sputter turned out to be the most effective way of cleaning C residues: C surface content after Ar sputter was reduced to or below the reference data (unetched sample). In terms of wet treatment, an optimized chemistry was identified (AltChem) and post-RIE cleaning was more efficient than dHF in reducing C surface concentrations.
We present a portable optical spectrometer for fugitive emissions monitoring of methane (CH4). The sensor operation is based on tunable diode laser absorption spectroscopy (TDLAS), using a 5 cm open path design, and targets the 2ν3 R(4) CH4 transition at 6057.1 cm-1 (1651 nm) to avoid cross-talk with common interfering atmospheric constituents. Sensitivity analysis indicates a normalized precision of 2.0 ppmv·Hz-1/2, corresponding to a noise-equivalent absorbance (NEA) of 4.4×10-6 Hz-1/2 and minimum detectible absorption (MDA) coefficient of αmin = 8.8×10-7 cm-1·Hz-1/2. Our TDLAS sensor is deployed at the Methane Emissions Technology Evaluation Center (METEC) at Colorado State University (CSU) for initial demonstration of single-sensor based source localization and quantification of CH4 fugitive emissions. The TDLAS sensor is concurrently deployed with a customized chemi-resistive metal-oxide (MOX) sensor for accuracy benchmarking, demonstrating good visual correlation of the concentration time-series. Initial angle-ofarrival (AOA) results will be shown, and development towards source magnitude estimation will be described.
The packaging of photonic devices remains a hindering challenge to the deployment of integrated photonic modules. This is never as true as for silicon photonic modules where the cost efficiency and scalability of chip fabrication in microelectronic production facilities is far ahead of current photonic packaging technology. More often than not, photonic modules are still packaged today with legacy manual processes and high-precision active alignment. Automation of these manual processes can provide gains in yield and scalability. Thus, specialized automated equipment has been developed for photonic packaging, is now commercially available, and is providing an incremental improvement in cost and scalability. However, to bring the cost and scalability of photonic packaging on par with silicon chip fabrication, we feel a more disruptive approach is required. Hence, in recent years, we have developed photonic packaging in standard, highthroughput microelectronic packaging facilities. This approach relies on the concepts already responsible for the attractiveness of silicon photonic chip fabrication: (1) moving complexity from die-level packaging processes to waferlevel planar fabrication, and (2) leveraging the scale of existing microelectronic facilities for photonic fabrication. We have demonstrated such direction with peak coupling performance of 1.3 dB from standard cleaved fiber to chip and 1.1 dB from chip to chip.
The impact of integrated photonics on optical interconnects is currently muted by challenges in photonic packaging and in the dense integration of photonic modules with microelectronic components on printed circuit boards. Single mode optics requires tight alignment tolerance for optical coupling and maintaining this alignment in a cost-efficient package can be challenging during thermal excursions arising from downstream microelectronic assembly processes. In addition, the form factor of typical fiber connectors is incompatible with the dense module integration expected on printed circuit boards. We have implemented novel approaches to interfacing photonic chips to standard optical fibers. These leverage standard high throughput microelectronic assembly tooling and self-alignment techniques resulting in photonic packaging that is scalable in manufacturing volume and in the number of optical IOs per chip. In addition, using dense optical fiber connectors with space-efficient latching of fiber patch cables results in compact module size and efficient board integration, bringing the optics closer to the logic chip to alleviate bandwidth bottlenecks. This packaging direction is also well suited for embedding optics in multi-chip modules, including both photonic and microelectronic chips. We discuss the challenges and rewards in this type of configuration such as thermal management and signal integrity.
The LER and LWR of subtractively patterned Si and SiN waveguides was calculated after each step in the process. It was found for Si waveguides that adjusting the ratio of CF4:CHF3 during the hard mask open step produced reductions in LER of 26 and 43% from the initial lithography for isolated waveguides patterned with partial and full etches, respectively. However for final LER values of 3.0 and 2.5 nm on fully etched Si waveguides, the corresponding optical loss measurements were indistinguishable. For SiN waveguides, introduction of C4H9F to the conventional CF4/CHF3 measurement was able to reduce the mask height budget by a factor of 5, while reducing LER from the initial lithography by 26%.
Phase change material (PCM)-based memory cells have shown promise as an enabler for low power, high density memory. There is a current need to develop and improve patterning strategies to attain smaller device dimensions. In this work, two methods of patterning of PCM device structures was achieved using directed self-assembly (DSA) patterning: the formation of a high aspect ratio pore designed for atomic layer deposition (ALD) of etch damage-free PCM, and pillar formation by image reversal and plasma etch transfer into a PCM film. We show significant CD reduction (180 nm to 20 nm) of a lithographically defined hole by plasma etch shrink, DSA spin-coat and subsequent high selectivity pattern transfer. We then demonstrate structural fabrication of both DSA-defined SiN pores with ALD PCM and DSA-defined PCM pillars. Challenges to both pore and pillar fabrication are discussed.
The need for continued device scaling along with the increasing demand for high precision have lead to the development of atomic layer etch processes in semiconductor manufacturing. We have tested this new methodology with regard to patterning applications. While these new plasma-enhanced atomic layer etch (PE-ALE) processes show encouraging results, most patterning applications are best realized by optimizations through discharge chemistry and/or plasma parameters. While PE-ALE approaches seem to have limited success for trilayer patterning applications, significant improvements were obtained when applying them to small pitch. In particular the increased selectivity to OPL seems to offer a potential benefit for patterning high aspect ratio features.
A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant patterning in the sub-30-nm pitch regime using directed self-assembly (DSA) line–space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck temperature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal–oxide–semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node.
We present a study on the optimization of etch transfer processes for circuit relevant patterning in the sub 30 nm pitch regime using directed self assembly (DSA) line-space patterning. This work is focused on issues that impact the patterning of thin silicon fins and gate stack materials. Plasma power, chuck temperature and end point strategy is discussed in terms of their effect on critical dimension (CD) control and pattern fidelity. A systematic study of post-plasma etch annealing processes shows that both CD and line edge roughness (LER) in crystalline Si features can be further reduced while maintaining a suitable geometry for scaled FinFET devices. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode and a SiN capping layer are also presented. We conclude with the presentation of a strategy for realizing circuit patterns from groups of DSA patterned fins. These combined results further establish the viability of DSA pattern generation as a potential method for CMOS integrated circuit patterning beyond the 10 nm node.
As 14nm node devices begin to permeate into the semiconductor industry, it is becoming increasingly evident that continued pitch scaling is getting more complex throughout the FEOL, MOL and BEOL. The adoption of patterning schemes and pitch splitting techniques such as double exposure/double etch and sidewall image transfer (SIT) are already underway to extend 193nm immersion lithography and enable 3D FinFET / Trigate devices. In addition, BEOL scaling of damascene copper is facing its own challenges, between the patterning and integration of porous ULK materials and the issue of increased resistivity emanating from grain boundary and surface scattering. As such, this paper will present work on novel etch methods envisioned to enable the successful extension of patterning and device integration for the 10nm node and beyond. Work related to the exploration of novel feedgas chemistries to extend etch performance for SiN spacer and oxide etch applications will be reviewed in detail. Specifically, the realization of a silicon nitride etch process which no longer depends on an oxidation mechanism, but rather a polymerization based etch mechanism will be shown. The process exhibits high selectivity to SiO2, Si and photoresist and results in reduced SOI loss while simultaneously maintaining all SiN on the gate sidewall and significantly reducing SiN footing. In addition, the feasibility of novel patterning methods such as the introduction of subtractive etching of copper will be reviewed in detail. Subtractive etching of Cu has the potential to overcome current interconnect integration difficulties by enabling blanket Cu film deposition with large grains, and by minimizing plasma damage during ULK etch, respectively. Successful patterning of copper at 25-50nm critical dimension (CD) with smaller than 100nm in pitch is demonstrated using a novel high density plasma based dry etch process.
S. Engelmann, R. Martin, R. Bruce, H. Miyazoe, N. C. Fuller, W. Graham, E. Sikorski, M. Glodde, M. Brink, H. Tsai, J. Bucchignano, D. Klaus, E. Kratschmer, M. Guillorn
CMOS device patterning for aggressively scaled pitches (smaller than 80nm pitch) faces many challenges. Maybe one of the most crucial issues during device formation is the pattern transfer from a soft mask (carbon based) material into a hard mask material. A very characteristic phenomenon is that mechanical failure of the soft material may be observed. While this was observed first for patterning below 80nm pitch, it becomes increasingly important for even smaller pitches (≤ 40 nm). Further process optimization
by various pre- and post-treatments has enabled robust pattern transfer down to 40nm
pitch. A systematic study of the parameters impacting this phenomenon will be shown.
Other challenges for patterning devices include profile control and material loss during
gate stack patterning and spacer formation. Lastly, initial patterning experiments at an
even more aggressive pitch show that the mechanical failure previously observed for
larger pitches once again becomes an increasingly important issue to consider.
Plasma-induced damage to low-k dielectric materials can be quantified by separation of the effects of charged-particle
bombardment, photon bombardment, and gas-radical flux. For ion and photon bombardment, the spatial location and
extent of the damage can be determined. Damage effects from radical flux will be shown to be small. Both SiCOH and
photo-programmable low-k (PPLK) dielectrics will be discussed.
Underlayers (UL), such as organic planarizing layers (OPLs) or spin-on carbon (SOC) layers, play a very important role
in various integration schemes of chip manufacturing. One function of OPLs is to fill in pre-existing patterns on the
substrate, such as previously patterned vias, to enable lithographic patterning of the next level. More importantly, OPL
resistance to reactive ion etch (RIE) processes used to etch silicon-containing materials is essential for the successful
pattern transfer from the resist into the substrate. Typically, the pattern is first transferred into the OPL through a two-step
RIE sequence, followed by the transfer into the substrate by a fluorine-containing RIE step that leaves the OPL
pattern mainly intact. However, when the line/space patterns are scaled down to line widths below 35 nm, it was found
that this last RIE step induces severe pattern deformation ("wiggling") of the OPL material, which ultimately prevents
the successful pattern transfer into the substrate.
In this work, we developed an efficient process to evaluate OPL materials with respect to their pattern transfer
performance. This allowed us to systematically study material, substrate and etch process parameters and draw
conclusions about how changes in these parameters may improve the overall pattern transfer margin.
KEYWORDS: Back end of line, Dielectrics, Etching, Lithography, Reactive ion etching, Photoresist materials, Optical lithography, Semiconducting wafers, Copper, Polishing
A novel back-end-of-line (BEOL) patterning and integration process termed Multi-Level Multiple Exposure
(MLME) technique is herein introduced. The MLME technique simplifies BEOL dual damascene (DD) integration while
simultaneously being applicable to all BEOL levels. It offers a patterning resolution reaching into the sub-100nm region
and improves semiconductor manufacturing cost and throughput. MLME employs a dual-layer imaging stack (via + trench resists) cast onto a customized etch transfer multilayer stack. This process implements a strict litho-litho-etch sequence for transferring the trench- and via-patterns into the dielectric layer. Under the MLME scheme, two imaging
steps (i.e. via- and trench-level patterning) are executed consecutively followed by a dry etch process that transfers the
lithographically-formed patterns into the customized etch transfer multilayer stack and further into the dielectric layer.
The MLME integration scheme not only decreases the number of overall process steps for the full DD BEOL process but
also eliminates several inter-tool wafer exchange sequences as performed in a conventional litho-etch-litho-etch process
flow. All MLME process steps were demonstrated i.e. combined 193nm-dry dual-resist layer MLME via- and trench-lithography,
full pattern transfer of via- and trench-patterns into the dielectric layer using reactive ion etching (RIE), as
well as electroplating and polishing of the DD patterns. This paper provides a detailed description of both post-lithography
steps of the DD process for a DD BEOL structure, i.e. (i) the RIE-pattern transfer process with the customized multilayer stack, and (ii) the metallization process completing the DD process for one BEOL layer.
Furthermore, the integration capabilities of the MLME technique were demonstrated and characterized by generating an
electrically functional via-chain connecting two neighboring BEOL layers fabricated by subsequently applying the MLME approach to both layers. An exhaustive description and evaluation of MLME lithographic patterning is given in an accompanying paper.
KEYWORDS: Optical lithography, Einsteinium, Back end of line, Etching, Dielectrics, Semiconducting wafers, Lithography, Photoresist materials, Nanoimprint lithography, Reactive ion etching
In this work, the conventional via-first dual damascene (DD) patterning scheme is replaced by a cost-efficient
Multi-Level Multiple Exposure (MLME) patterning and etching approach. A two-layer positive-tone photoresist stack is
sequentially imaged using 193 nm dry lithography, to produce a DD resist structure that is subsequently transferred into
an auxiliary dual organic underlayer stack, and then further into a dielectric layer. This novel integration approach
eliminates inter-tool wafer exchange sequences as performed in a conventional litho-etch-litho-etch process flow, while
simultaneously being applicable to all back-end-of-the-line (BEOL) levels, ensuring throughput increase. The top and
bottom resist layers are chemically designed in such a way that they feature differential solubility in organic solvents
making it possible to coat the top photoresist onto the bottom resist layer without intermixing to enable a strict litholitho-
etch processing sequence. Independent registration of the via and trench structures in the bottom and top resist
layers is achieved by selective photospeed decoupling of the respective layers, so that the bottom resist is largely
insensitive at nominal resist exposure dose for the top resist. Imaging performance evaluation of the newly introduced
MLME technology includes the resist materials selection process and their required properties (solvent compatibility,
adhesion, photospeed, defectivity and correction of via dose bias due to trench exposure) as well as metrology work.
Image transfer of the patterned DD resist structure into an underlying transfer layer stack and then further into a
dielectric layer using Reactive Ion Etching (RIE) followed by electroplating, polishing and electrical testing was also
thoroughly investigated and is described in detail in an accompanying paper.
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