As the design rule of Integrated Circuits(IC) becomes smaller, the precise measurement of Critical Dimension (CD) of
features and minimization of deviation in CD measured becomes a vital issue. In this paper, a simple frequency analysis
method to extract the noise from SEM images was used to evaluate the contribution of SEM noise in CD Uniformity.
Multiple SEM images of simple Line and Space (L/S) patterns were analyzed and a model of frequency profile (Power
Spectrum Density (PSD) model) was made using an offline analyzing tool based on Matlab®. From this profile, white
noise and 1/f profile were separated. Noises are eliminated to generate a noise reduced PSD profile to make CD results.
The contribution of white noise on CD measurement can be assessed using Line Width Roughness (LWR) measurement.
Furthermore, CD uniformity can be also predicted from the model. This prediction is based on an assumption that CD
uniformity is equal to LWR if the inspection area is extended to infinity and appropriate sampling method is applied. The
results showed that the contribution of white noise on LWR can be up to around 70% (in power) without any noise
reduction measures (sum line averaging) after imaging in photo resist image. For experimental validation, CD uniformity
is predicted from the model for different measurement conditions and compared with real measurement. For a result, CD
uniformity prediction (3sigma) from the model shows within 20% in accuracy with real CD uniformity value measured
from the photo resist image.
Recent advances in EUVL lithography is mainly centered on improving the RLS trade-off by employing new resist
platforms, bulkier PAGs, EUV sensitizers etc. Among the several new kinds of PAGs proposed till date, the focus of
development was mainly on the acid strength, compatibility with resin etc., whilst always retaining the mono, Di or tri
phenyl chromophore of the PAG. Herein we report on the use of chromophore-less PAG for the patterning of EUVL
resists. Resist performance using model acrylate and PHS based resist was studied. The patterned resists were
characterized using SEM. Thermal stability of the PAG was compared with model chromophore containing PAG.
In this paper we investigate fundamental resist properties to enhance resolution and focus margin for immersion
contact hole patterning. Basic chemistry factors have been used to manipulate the iso-focal region (the region of
smallest critical dimension variation through focus) of the photoresist and study the impact on resolution and focus
margin for small isolated contact holes. Acid diffusion length is one of the key factors investigated, which can be
controlled by polymer, PAG, quencher, bake temperature and bake time. The various criteria investigated for this study
were: focus and exposure latitude for dense L/S, dense C/H and semi-dense C/H. The effect of manipulating the acid diffusion of the photoresist on imaging small contact holes was verified using ultra-high NA immersion imaging at 1.35
NA.
KEYWORDS: Reflectivity, Lithography, Critical dimension metrology, Line width roughness, Immersion lithography, Optical lithography, Photomasks, Scanning electron microscopy, Electroluminescence, Control systems
Reflectivity comparison study of bottom anti reflectivity coating (BARC) was investigated at 30nm node devices with same gate width at different pitch sizes. The goal of this study is to elucidate the practical target of reflectivity for high NA immersion lithography especially focusing on the changes in the CD variation. Using double patterning technology (DPT) and single patterning technology (SPT) patterns in high NA systems, we studied the impact of reflectivity to the lithography performance for various ARC thicknesses.
A strong dependence of n, k values (of BARC and substrate) on reflectivity was confirmed by simulation. Standing wave effects were investigated by vertical profiles inspection and changes in lithographic performances. Finally, we investigated the critical dimension uniformity (CDU), and line width roughness (LWR) variations for various reflectivities using hard mask substrates. Our experimental and simulation results clearly show that a 0.1% reflectivity target is highly recommendable for the sub-30 nm device process using high NA immersion lithography.
Many issues need to be overcome in creating a production-worthy sub-k1 (<0.25) process. The
repeating photo-etch sequential method for clear and dark mask type is susceptible to overlay
issues while accuracy of first pattern is critical for the space technology. Both technologies
require improved model accuracy and process margin. Because of this, even traditionally noncritical
regions of a layout may contain process margin-limiting defects for double patterning
technology. An integrated OPC-Verification-Selective OPC procedure is developed to improve
quality of results for non-critical regions while retaining fast TAT. The first step utilizes a fast
OPC method with reduced TAT. Next, a lithographic verification tool is used to perform a
thorough check of the OPC results, including process window analysis. This determines which
points limit process margin. Finally, advanced OPC methods are applied to reprocess the areas
limiting process margin. These advanced OPC techniques may include broader lithographic
analysis, field-based correction and process window consideration. Since advanced OPC
methods are only applied to part of the design, TAT is fast. TAT can be further improved by
treating critical regions differently. Critical regions will not be processed in the initial OPC or
intermediate verification steps, but will be corrected by the advanced OPC methods. This
methodology is called Incremental OPC as it applies the most appropriate OPC techniques to
each area of the design. As a result, process margin limiting defects, side-lobe printing and subresolution
assist feature printing can be eliminated prior to mask tape-out with minimal impact
to TAT. In this paper, Incremental OPC is compared to "all-or-nothing" OPC techniques which
must be applied across an entire pattern.
In this paper, two different methods of double exposure are proposed to improve the resolution in low k1 lithography. One is using an additional mask to complement the lack of image contrast. The other is to fix the mask and only use combinations of illumination systems to increase image contrast. By applying image assisting double exposure to asymmetry dense contact under k1=0.33, the process window can be doubled in comparison to the single exposure method. By an appropriate design of two masks, we could also minimize the image distortion from overlay shift by mixture of masks. Effective first order efficiency is defined as a new term in double exposure with complementary illumination. The larger the value is, the better the image contrast becomes. Through an experiment and simulation in k1=0.30, in double exposure with two illuminations and the same mask, that wider process window was obtained than in single exposure with optimized illumination system, and also 0.10um of DOF (Depth of Focus) was obtained under k1=0.28.
As k1 factor approaches the theoretical limit, optical proximity correction (OPC) treatments necessary to maintain dimensional tolerances involve increasingly complex correction shapes. This translates to more detailed, or larger mask pattern databases. Moreover, development of exposure tools lags behind the shrinkage of device. This may result in dwindling of process margin in lighographic process despite using all possible resolution enhancement techniques (RETs). Although model-based OPC may lose its effectiveness in case of narrower photolithographic process margin, model-based OPC is recognized as a robust tool to cope with the diversity of layout. By the way, in case of narrower photolithographic process margin, model-based OPC lose its effectiveness. To enhance the usefulness of the OPC, we need to overcome many obstacles. It is supposed that the original layout be designed friendly to lithography to enhance the process margin using aggressive RETs, and is amended by model-based OPC to suppress the proximity effect. But, some constraints are found during an OPC procedure. Ultimately, unless the original lithgraphy friendly layout (LFL) is corrected in terms of pitches and shapes, the lithography process is out of process window as well as makes pattern fidelity poor. This paper emphasizes that the application of model-based OPC requires a particular and unique layout configuration to preserve the process margin in the low k1 process.
As DRAM (Dynamic Random Access Memory) device continuously decreases in chip size, an increased speed and more accurate metrology technique is needed to measure CD (critical dimension), film thickness and vertical profile. Scatterometry is an optical metrology technique based on the analysis of scattered (or diffracted) light from periodic line and space grating and uses 2θ angular method (ACCENT Optical Technologies CDS-200). When a light source is irradiated into the periodic pattern, the scattered intensity signal of zero-th order as a function of incident angle is measured. By analyzing these scattered signals, various parameters of the periodic pattern such as CD, vertical profile, mapping of substrate structure, film thickness and sidewall angle can be determined. Advantages of scatterometry are that drastic decreased measuring time and acquirement of CD, vertical profile, film thickness and sidewall angle by just one measurement. In this paper we will discuss various applications of scatterometry to sub-100nm DRAM structures of straight line and space and curved line and space patterns. Details of the correlation with CD-SEM (Scanning Electron Microscope) of standard metrology tool and repeatability of measured CD values will be discussed. As diverse applications, results of in-field, in-wafer and wafer-to-wafer CD monitoring, STI (Shallow Trench Isolation) depth monitoring and matching of vertical profile with V-SEM (Vertical SEM) will be also presented.
ArF lithography has been successfully implemented for the development of sub-90nm DRAM devices. Line width control for the ArF lithography is becoming increasingly challenging as design rules shrink. Many works have been performed on the mask, exposure tools, and tracks to obtain better critical dimension (CD) uniformity, however in-field uniformity, in-wafer uniformity, and wafer-to-wafer uniformity from resist itself was not considered thoroughly. In this experiment, resist parameters that contributes to line width variation were considered in resist perspective. For the in-field uniformity, mask CD uniformity is very important. However, the mask error enhancement factor (MEEF) was different ranging from 3.27 to 5.12 depending on the resists in the k1 0.35 processes even though the screened resists met all the required resolution, depth of focus (DOF), exposure latitude (EL), line edge roughness (LER), and profile. For the resists having good MEEF, the in-filed uniformities of the critical layers were highly improved. The PEB sensitivities of the screened resists were evaluated again in terms of post exposure bake (PEB) sensitivity, which were quite higher than those of KrF resists. They ranged from 4.0 to 11.3 nm/°C. In-wafer uniformity was evaluated and compared using the resists having different PEB sensitivity. The resist with better PEB sensitivity showed better result in in-wafer uniformity. Finally, the wafer-to-wafer uniformities of the resists were evaluated. There was different delay after exposure depending on the sequence of the loaded wafers because it was not easy to control the delay time at the interface of a scanner and a track. The CD increased depending on the sequence, and it coincided well with the delay time of the wafers after exposure. The wafer-to-wafer CD variations were improved using the resists having strong resistance to the delay.
As the design rule of device has shrunken, obtaining a feasible process window at low k1 factor in photolithography is the major concerning in order to shorten the total period from development to the mass production of devices. In this low k1 factor region, a tiny CD variation on mask might be increased abruptly on the wafer. In particular, such variation so called MEEF (Mask Error Enhancement Factor) is closely related with various types of process parameter. In this paper, we reviewed optimized process condition to minimize MEEF and defined uDoF (Usable Depth of Focus) considering a correlation between MEEF and DoF (Depth of Focus).
Understanding the nature of photo-resist (PR) dissolution during the development process is the important factor to accomplish high-precision critical dimension (CD) control in photolithography. In this report, we investigate the effect of each process variable on the PR pattern CD size and surface roughness by scanning electron microscopy (SEM) and atomic force microscopy (AFM). From these experiments, we found out that the major factor to affect the CD and surface roughness control was the puddle time. On the basis of these result, we investigated the relationship between puddle time and chemical compositions of PR. According to the puddle time, top surface of PR became rougher, but finally converged to some value. As the molecular weight and protecting ratio of the PR increased, the degree of surface roughness of the PR increased. Soft bake temperature, which is one of the variables in PR coating process, also affected the surface roughness of the PR. These results must be useful data for the optimization of new developing recipe for the new PR systems which will achieve next generation photolithography.
For higher density devices electric performances have been focused more than the others. In the case of metal sputtering process some of machine makes local asymmetric deposition across the wafer. In this study, a couple of overlay reading errors which comes from asymmetric metal deposition has been studied in terms of photo process. As a result, scaling error could be reduced down to a certain amount with the optimization of overlay reading marks. However it will not be cleared no matter what kinds of mark are used as long as overlay marks are asymmetry. A symmetric sputtering should be the only way to figure out this problem. In order to make total product, related processes have to be concerned as well.
Currently it is very popular to use off-axis illumination technique for higher resolution with wider depth of focus. However there are several problems in the technique, one of which is deterioration of image quality induced by the non- uniform effective source distribution. If the intensity distribution on the illumination aperture lacks of spatial symmetry, each diffraction order beam impinging on the wafer surface has angularly asymmetric distribution. This makes the optical system have pattern size dependent telecentricity error. For a simple line or grouped lines it gives rise to only the pattern displacement with defocus which can hardly be detected unless there are any reference. But the periodic island type patterns which have discrete features and multiple pitch components in one direction can be bent and deformed asymmetrically with defocus. Asymmetric imaging for island type patterns gives rise to also the pattern CD asymmetry with defocus. We present schematic explanation of the effects of non-uniform effective source and the simulation result. We also investigated the phenomena in a high density DRAM cell active layer of 460 nm minimum pitch and characterized it by various approach.
We report the results of an investigation into the quality of overlay data obtained from a chemical-mechanical polish (CMP) process. The limiting step height for standard bright field optical imaging is examined and found to be less than 200 angstrom. Tool repeatability improvements are demonstrated using a mixture of imaging system modifications and image processing techniques. Using these it is possible to achieve very repeatable data. Good tool precision is insufficient evidence of good data quality as the process can distort the target so that it does not accurately measure the stepper overlay error. We report an examination of data quality obtained using different target designs and both with and without an additional etch- back step to enhance the contrast of the image being measured. Several different techniques have been applied to determine whether the data is accurate. We conclude that bar and frame type targets give much more accurate results than traditional box styles. In addition the tool performance is also improved by using the same target designs. With this choice of target design accurate data is obtained and meaningful correction of stepper errors becomes possible.
In this paper, we present methods of eliminating an overlay scaling error which is introduced when multi-layer resist (MLR) structures are imaged with a narrow bandwidth light source. Using the conventional box-in-box type mark, an intense interference fringe is produced around the box type mark and results in a scaling error on overlay reading. An optical interference effect combined with resist build-up of bottom PR is the origin of the scale error. Two methods have been tried to find a solution without changing the process. To remove the interference effects, a broad bandwidth light source was adopted so that clean and uniform images are obtained. On the other hand, to eliminate the resist build-up, narrow bar marks corresponding to the large box pattern have been generated to reduce the effect with the narrow bandwidth light source. Using the above methods we could realize accurate overlay measurement on MLR structures. The changes have been applied to a real DRAM process.
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