This paper presents an 8 channel ASIC for SiPM anode readout based on a novel low input impedance current conveyor (under patent1). This Multiple Use SiPM Integrated Circuit (MUSIC) has been designed to serve several purposes, including, for instance, the readout of SiPM arrays for some of the Cherenkov Telescope Array (CTA) cameras. The current division scheme at the very front end part of the circuit splits the input current into diﬀerently scaled copies which are connected to independent current mirrors. The circuit contains a tunable pole zero cancellation of the SiPM recovery time constant to deal with sensors from diﬀerent manufacturers. Decay times up to 100 ns are supported covering most of the available SiPM devices in the market. MUSIC oﬀers three main features: (1) diﬀerential output of the sum of the individual input channels; (2) 8 individual single ended analog outputs and; (3) 8 individual binary outputs. The digital outputs encode the amount of collected charge in the duration of the digital signal using a time over threshold technique. For each individual channel, the user must select the analog or digital output. Each functionality, the signal sum and the 8 A/D outputs, include a selectable dual-gain conﬁguration. Moreover, the signal sum implements dual-gain output providing a 15 bit dynamic range. Full die simulation results of the MUSIC designed using AMS 0.35 µm SiGe technology are presented: total die size of 9 mm2, 500 MHz bandwidth for channel sum and 150 MHz bandwidth for A/D channels, low input impedance (≈32 Ω), single photon output pulse width at half maximum (FWHM) between 5 and 10 ns and with a power consumption of ≈ 30 mW/ch plus ≈ 200 mW for the 8 ch sum. Encapsulated prototype samples of the MUSIC are expected by March 2016.
A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different layout design implementations. Moreover, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the parametric yield and increases the number of good dies per wafer.
A yield estimation model to evaluate the lithography distortion in a printed layout is presented. The yield model relates the probability of non-failure of a lithography hotspot with the manufacturing yield loss. We define a lithography hotspot as a pattern construct with excessive variation under lithography printing using lithography simulations. Thereby, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho-degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the manufacturing yield and increases the number of good dies per wafer.