Currently advanced DRAM design is beyond ArFi resolution limit, especially for the challenging processes in memory cell and core circuit pattern . When devices keep shrinking, multi-patterning with ArFi becomes more and more difficult to reach the process requirements in terms of pattern decomposition, process window loss with complex process integration, defect, and immersion resolution limits. Besides multi-patterning also suffers design cost, mask learning cycle and layout restriction. Currently 0.33NA EUV can provide 16nm pattern single exposure and cover all design circuit requirement. High resolution enhances 2D pattern process window for friendly layout design and better OVL control so it is a good choice to introduce EUV process for DRAM manufacturing.
We evaluate to apply EUV in memory cell instead of the two possible solutions of SADP with cut layer and LELE trimming with multi-mask to simplify processes. Memory cell is periodic main feature for the most area on a mask and dominates the most EUV OPC run time in full shot correction. In this paper we try to find a best way to handle cell area OPC and evaluate single mask to accomplish memory cell patterning.
Memory cells and access structures consume a large percentage of area in embedded devices so there is a high return from shrinking the cell area as much as possible. This aggressive scaling leads to very difficult resolution, 2D CD control and process window requirements. As the scaling drives lithography even deeper into the low-k1 regime, cooptimization of design layout, mask, and lithography is critical to deliver a production-worthy patterning solution. Computational lithography like Inverse Lithography Technology (ILT) has demonstrated it is an enabling technology to derive improved solutions over traditional OPC as reported in multiple prior publications. In this paper, we will present results of a study on advanced memory cell design optimization with Cell-Level ILT (CL-ILT) where significant design hierarchy can be retained during ILT optimization. Large numbers of cell design variations are explored with automatically generated patterns from ProteusTM Test Pattern Generator (TPG). Fully automated flows from pattern generation to mask synthesis with ILT, data analysis and results visualization are built on ProteusTM Work Flow (PWF) for exploring a fully parameterized design space of interest. Mask complexity including assist features (AF) types, rule or model based, and main feature segmentation are also studied to understand the impact on wafer lithographic performance. A heatmap view of results generated from this design exploration provides a clear and intuitive way to identify maximum design limits of memory cells. Comparison of results from ILT and traditional OPC will be presented as well with both wafer and simulation data.
As feature sizes and pitches continue to decrease, more complex correction algorithms are needed to solve increasingly difficult geometric configurations. Usage of these more complex algorithms results in unacceptably long time-to-mask when applied to an entire design. In many cases, the more complex algorithms are only required in a small percentage of areas of the entire design, and these areas are not always known prior to tapeout. Hotspot fixing (HSF) flows are increasingly used to fix these hotspot areas to minimize errors and decrease time-to-mask. These flows involve “recorrecting” a design, using the previous correction output as the input to the HSF flow. This input file contains a hierarchy that was optimized for the original correction. Hotspot areas are frequently smaller than the original correction areas and frequently repeat in unique cell outputs of the original correction, so the optimal hierarchy for a HSF fix flow may be very different from the original correction. A new hierarchy, optimized for HSF, is difficult to form from the corrected output. This paper describes the usage of pattern-matching to regain hierarchical compression for identical hotspot areas that are not repeating cells in the original correction. Using this pattern-matching HSF flow, turnaround time for the hotspot fixing can be more than 50X faster than re-using the original correction’s hierarchy for complex HSF methods. These significant gains can be achieved in spite of the additional complexity it can add to the flow. In the case where simpler/faster HSF correction methods are used, significant turnaround time gains can still be made by using this pattern matching technique.
Hotspot fixing methodologies are increasingly deployed during tapeouts as a means to optimize the tradeoffs between complex, highly accurate correction methods and faster methods that are sufficient for most pattern areas.1 However, pattern database hierarchies may not be optimum for these hotspot fixing flows, as they are optimized for the initial correction run or method. This paper examines the usage of pattern matching to regain hierarchy and significantly reduce turn-around-time for complex hotspot fixing methods. Gains in turn-around-time can be well over 50 times faster than reusing the original correction’s hierarchy.
Model-driven target optimization using an ILT hotspot fixer is applied to line collapsing defects of 2-
dimensional randomtest pattern of a very low K1 process. The target is moved by minimizing the process
variation band and the pitches of hotspot points are relaxed.The image quality improvement is thenchecked.
Model driven target optimized NILS and MEEF at the weakest hotspot point are improved to 1.22 and 5.5
from the values 0.79 and 10.6 of a traditional OPCwith advanced solver, respectively. The pattern collapsing
hotspot is then validated to be repaired by optimizing target position. A full hotspot fixer flow including
model-driven target optimization using ILT can also be extended into DFM applications.
Although the mask pattern created by fine ebeam writing is four times larger than the wafer pattern, the mask
proximity effect from ebeam scattering and etch is not negligible. This mask proximity effect causes mask-CD errors and consequently wafer-CD errors after the lithographic process. It is therefore necessary to include
the mask proximity effect in optical proximity correction (OPC). Without this, an OPC model can not predict
the entire lithography process correctly even using advanced optical and resist models. In order to compensate
for the mask proximity effect within OPC a special model is required along with changes to the OPC flow.
This article presents a method for producing such a model and OPC flow and shows the difference in results
when they are used.
Proc. SPIE. 5567, 24th Annual BACUS Symposium on Photomask Technology
KEYWORDS: Lithography, Etching, Scanning electron microscopy, Process control, Photomasks, Critical dimension metrology, Photoresist processing, Semiconducting wafers, Standards development, Picture Archiving and Communication System
In previous study the high impact of development by-products on Critical Dimension (CD) through the microloading effect has been demonstrated for a Novolak resist. In this paper, through further tests involving Chemically Amplified Resist (CAR) and Novolak resist, the microloading effect of development is characterized and tentative mechanism is presented.
Megasonic Immersion Development (MID), a high flow rate development technique similar to the Proximity Gap Suction Development (PGSD), was used and compared with spin spray development and puddle development.
On TOK IP3600, a Novolak resist, we have explored a wide range of process conditions with MID. Developer temperature was varied from 5°C to 40°C with TMAH developer concentration of 1.9% and 2.38% resulting in an isofocal dose range of 90mJ to 190mJ. Exposure Focus Matrix (EFM) with a specific microloading pattern and resist cross sections were performed. The best conditions are quite far from the standard process advised by the resist supplier. Very nice standing wave profile was obtained at high temperature development.
On CAR, JEOL 9000MVII, a 50kV e-beam vector scan tool, and ETEC ALTA 4300, a DUV raster scan tool, were used with different develop process techniques including MID. FujiFilm Arch FEP-171 positive CAR and Sumitomo NEB-22 negative CAR were used on 50kV writing tool. Sumitomo PEK-130 was used on DUV writing tool. FEP-171 and PEK-1300 show microloading effect on high density patterns but not NEB-22.
MID shows also improved reproduction of develop features in the chrome and a 20% improvement of CD uniformity. The results of this study seem to indicate that a closer look in their development process is needed for 90nm and 65nm technologies.
The move towards smaller feature size continuously requires more accurate lithography models. Part of models improvement comes from a better understanding of involved physics and chemistry. State of the art models assume development rate to be dependent on level of de-protection of resist film while development kinetics is not taken into account. Model refinements consist in getting a good model of development rate versus de-protection level. Recent studies have put in evidence the importance and the influence of development kinetics. Based on this, a new development process concept has been developed: the Proximity Gap Suction Development (PGSD). This paper presents a parallel approach to PGSD using megasonic agitation in order to improve development process understanding. Analysis has been performed by focusing on microloading effect characterization, also taking into account Critical Dimension (CD) linearity, CD iso-dense bias. Interpretation and analysis were achieved through use of DOE techniques. Results are then discussed with respect to previous PGSD studies but also to current development models. It is believed that improvement of development process could be also achieved in wafer making through the use of high flow rate development techniques such as PGSD or megasonic development.
Recently there has been significant interest in the using of chemically amplified (CA) resists for the mask making industry because of their high sensitivity, high contrast, and good dry etch resistance. Especially positive CA resists with high acceleration voltage E-beam systems are being become the main stream of making for advanced masks. However, the positive CA resists often make the issue of the CD uniformity degradation by the fogging effect at a high acceleration voltage (50keV) E-beam writing tool as writing for masks, which are having a high pattern density. In previous our paper, we have already confirmed that a positive CA resist shows the CD uniformity error more than 30nm by the fogging effect at the mask which is having above 40% pattern density, even if its CD uniformity error value is smaller than 50nm of ZEP. In this paper, we have described and studied for the performances of the negative CA resist at the 50keV e-beam writing tools in advanced mask making like logic device with high pattern density and we have compared with a positive CA resist at the 50keV e-beam writing tools. Furthermore, we have confirmed that the negative CA resist have an advantage
what is in advanced mask making process like logic device masks with high pattern density at 50keV e-beam writing tool and they have been compared with the positive CA resist.
As the CD specification on Masks is getting more tighten, the fogging effect by re-scattered incident electron at a high acceleration e-beam system and the loading effect at dry etching step due to pattern density are current critical issues for mask making. These give rise to the variation of mean CD value and the degradation of global CD uniformity. So we have to correct these effects accurately in order to meet the CD specification for design rule 0.15um or below devices. In this paper, we have applied a new positive CA (chemically amplified) resist from Fuji Film Arch co., It was written at 50 kV variable vector scan E-beam system and we tried to classify the CD error by the fogging and loading effect, respectively. Also we have compared with ZEP7000 resist, non-CAR positive type, which is used widely for conventional e-beam mask making to assess the CAR performance, especially in terms of CD error causing by the fogging effect. Through this comparison test, we found that the CD error due to the fogging effect shows somewhat different value according to resist type and writing strategy even though use same exposure dose. In this paper, we have assumed that such results are due to the difference of dose latitude. Dose latitude is different as intrinsic contrast value of each resist and writing strategy such as writing pass, should affect on beam profile (dose profile), it can also change pattern profile of resist and it can finally cause a dose latitude difference. Finally, we have evaluated for CD mean error and uniformity error by fogging and etch loading as open ratio changing, respectively.