Mr. Shawn H. Lee Profile

Shawn H. Lee

at ASML Netherlands BV

SPIE Involvement:

Author

Publications (10)

Proceedings Article | 20 March 2019 Paper

Holistic feedforward control for the 5 nm logic node and beyond

Henry Megens, Ralph Brinkhof, Igor Aarts, Haico Kok, Leendertjan Karssemeijer, Gijs ten Haaf, Shawn Lee, Daan Slotboom, Chris de Ruiter, Irina Lyulina, Simon Huisman, Stefan Keij, Evert Mos, Wim Tel, Manouk Rijpstra, Emil Schmitt-Weaver, Kaustuve Bhattacharyya, Robert Socha, Boris Menchtchikov, Michael Kubis, Jan Mulkens

Proceedings Volume 10961, 109610K (2019) https://doi.org/10.1117/12.2515449

KEYWORDS: Lithographic process control, Semiconducting wafers, Optical alignment, Overlay metrology, Sensors, Distortion, Scanners, Logic, Metrology, Process control

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Proceedings Article | 24 March 2017 Paper

Novel methodology to optimize wafer alignment to enhance 14nm on product overlay

Pavan Samudrala, Woong Jae Chung, Lokesh Subramany, Haiyong Gao, Nyan Aung, Seung Chul Oh, Shawn Lee, Erik Delvigne, Blandine Minghetti

Proceedings Volume 10147, 101471U (2017) https://doi.org/10.1117/12.2258137

KEYWORDS: Optical alignment, Overlay metrology, Scanners, Yield improvement, Lithium, Data modeling, Roads

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Proceedings Article | 21 April 2016 Paper

Analysis of wafer heating in 14nm DUV layers

Lokesh Subramany, Woong Jae Chung, Pavan Samudrala, Haiyong Gao, Nyan Aung, Juan Manuel Gomez, Blandine Minghetti, Shawn Lee

Proceedings Volume 9778, 97780U (2016) https://doi.org/10.1117/12.2218724

KEYWORDS: Semiconducting wafers, Overlay metrology, Deep ultraviolet, Scanners, Process control, Photomasks, Reticles, Metrology, Metals, Data modeling, Image enhancement

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Proceedings Article | 24 March 2016 Paper

Focus control enhancement and on-product focus response analysis methodology

Young Ki Kim, Yen-Jen Chen, Xueli Hao, Pavan Samudrala, Juan-Manuel Gomez, Mark Mahoney, Ferhad Kamalizadeh, Justin Hanson, Shawn Lee, Ye Tian

Proceedings Volume 9778, 97780T (2016) https://doi.org/10.1117/12.2213019

KEYWORDS: Error analysis, High volume manufacturing, Semiconducting wafers, Metrology, Process control, Control systems, Scanners, Diffraction, Time metrology, Forward error correction, Lithography, Critical dimension metrology

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Proceedings Article | 15 March 2016 Paper

CDU budget breakdown as a diagnostic method for imaging sensitivity in HVM

Young Ki Kim, Pavan Samudrala, Juan-Manuel Gomez, Peter Nikolsky, Roy Anunciado, Maria Barkelid, Shawn Lee, Ye Tian, Justin Hanson

Proceedings Volume 9780, 97801Q (2016) https://doi.org/10.1117/12.2214123

KEYWORDS: Semiconducting wafers, Reticles, Critical dimension metrology, Scanners, Photomasks, Metrology, Laser processing, Laser scanners, 3D scanning, Laser metrology

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SPIE Journal Paper | 18 March 2013

Mask characterization for critical dimension uniformity budget breakdown in advanced extreme ultraviolet lithography

Peter Nikolsky, Chris Strolenberg, Rasmus Nielsen, Tjitte Nooitgedacht, Natalia Davydova, Greg Yang, Shawn Lee, Chang-Min Park, Insung Kim, Jeongho Yeo

JM3, Vol. 12, Issue 02, 021006, (March 2013) https://doi.org/10.1117/12.10.1117/1.JMM.12.2.021006

KEYWORDS: Photomasks, Reticles, Critical dimension metrology, Semiconducting wafers, Extreme ultraviolet lithography, Extreme ultraviolet, Cadmium, Reflectivity, Scanners, Semiconductors

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As the International Technology Roadmap for Semiconductors critical dimension uniformity (CDU) specification shrinks, semiconductor companies need to maintain a high yield of good wafers per day and high performance (and hence market value) of finished products. This cannot be achieved without continuous analysis and improvement of on-product CDU as one of the main drivers for process control and optimization with better understanding of main contributors from the litho cluster: mask, process, metrology and scanner. We will demonstrate a study of mask CDU characterization and its impact on CDU Budget Breakdown (CDU BB) performed for advanced extreme ultraviolet (EUV) lithography with 1D (dense lines) and 2D (dense contacts) feature cases. We will show that this CDU contributor is one of the main differentiators between well-known ArFi and new EUV CDU budgeting principles. We found that reticle contribution to intrafield CDU should be characterized in a specific way: mask absorber thickness fingerprints play a role comparable with reticle CDU in the total reticle part of the CDU budget. Wafer CD fingerprints, introduced by this contributor, may or may not compensate variations of mask CDs and hence influence on total mask impact on intrafield CDU at the wafer level. This will be shown on 1D and 2D feature examples. Mask stack reflectivity variations should also be taken into account: these fingerprints have visible impact on intrafield CDs at the wafer level and should be considered as another contributor to the reticle part of EUV CDU budget. We also observed mask error enhancement factor (MEEF) through field fingerprints in the studied EUV cases. Variations of MEEF may play a role towards the total intrafield CDU and may need to be taken into account for EUV lithography. We characterized MEEF-through-field for the reviewed features, with results herein, but further analysis of this phenomenon is required. This comprehensive approach to quantifying the mask part of the overall EUV CDU contribution helps deliver an accurate and integral CDU BB per product/process and litho tool. The better understanding of the entire CDU budget for advanced EUVL nodes achieved by Samsung and ASML helps extend the limits of Moore’s Law and to deliver successful implementation of smaller, faster and smarter chips in semiconductor industry.

Proceedings Article | 8 November 2012 Paper

Mask characterization for CDU budget breakdown in advanced EUV lithography

Peter Nikolsky, Chris Strolenberg, Rasmus Nielsen, Tjitte Nooitgedacht, Natalia Davydova, Greg Yang, Shawn Lee, Chang-Min Park, Insung Kim, Jeong-Ho Yeo

Proceedings Volume 8522, 85220P (2012) https://doi.org/10.1117/12.970395

KEYWORDS: Photomasks, Reticles, Semiconducting wafers, Extreme ultraviolet, Extreme ultraviolet lithography, Critical dimension metrology, Scanners, Reflectivity, Cadmium, Semiconductors

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As the ITRS Critical Dimension Uniformity (CDU) specification shrinks, semiconductor companies need to maintain a high yield of good wafers per day and a high performance (and hence market value) of finished products. This cannot be achieved without continuous analysis and improvement of on-product CDU as one of the main drivers for process control and optimization with better understanding of main contributors from the litho cluster: mask, process, metrology and scanner. In this paper we will demonstrate a study of mask CDU characterization and its impact on CDU Budget Breakdown (CDU BB) performed for an advanced EUV lithography with 1D and 2D feature cases. We will show that this CDU contributor is one of the main differentiators between well-known ArFi and new EUV CDU budgeting principles. We found that reticle contribution to intrafield CDU should be characterized in a specific way: mask absorber thickness fingerprints play a role comparable with reticle CDU in the total reticle part of the CDU budget. Wafer CD fingerprints, introduced by this contributor, may or may not compensate variations of mask CD’s and hence influence on total mask impact on intrafield CDU at the wafer level. This will be shown on 1D and 2D feature examples in this paper. Also mask stack reflectivity variations should be taken into account: these fingerprints have visible impact on intrafield CDs at the wafer level and should be considered as another contributor to the reticle part of EUV CDU budget. We observed also MEEF-through-field fingerprints in the studied EUV cases. Variations of MEEF may also play a role for the total intrafield CDU and may be taken into account for EUV Lithography. We characterized MEEF-through-field for the reviewed features, the results to be discussed in our paper, but further analysis of this phenomenon is required. This comprehensive approach to characterization of the mask part of EUV CDU characterization delivers an accurate and integral CDU Budget Breakdown per product/process and Litho tool. The better understanding of the entire CDU budget for advanced EUVL nodes achieved by Samsung and ASML helps to extend the limits of Moore's Law and to deliver successful implementation of smaller, faster and smarter chips in semiconductor industry.

Proceedings Article | 5 April 2007 Paper

The application of SMASH alignment system for 65-55-nm logic devices

M. Miyasaka, H. Saito, T. Tamura, T. Uchiyama, Paul Hinnen, Hyun-Woo Lee, Marc van Kemenade, Mir Shahrjerdy, Robert van Leeuwen

Proceedings Volume 6518, 65180H (2007) https://doi.org/10.1117/12.711059

KEYWORDS: Optical alignment, Diffraction, Overlay metrology, Sensors, Signal processing, Semiconducting wafers, Optical design, Signal detection, Diffraction gratings, Manufacturing

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Proceedings Article | 5 April 2007 Paper

Advances in process overlay: alignment solutions for future technology nodes

Henry Megens, Richard van Haren, Sami Musa, Maya Doytcheva, Sanjay Lalbahadoersing, Marc van Kemenade, Hyun-Woo Lee, Paul Hinnen, Frank van Bilsen

Proceedings Volume 6518, 65181Z (2007) https://doi.org/10.1117/12.712149

KEYWORDS: Optical alignment, Semiconducting wafers, Overlay metrology, Photomasks, Metrology, Polarization, Refractive index, Signal detection, Semiconductors, Lithography

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Semiconductor industry has an increasing demand for improvement of the total lithographic overlay performance. To improve the level of on-product overlay control the number of alignment measurements increases. Since more mask levels will be integrated, more alignment marks need to be printed when using direct-alignment (also called layer-to-layer alignment). Accordingly, the alignment mark size needs to become smaller, to fit all marks into the scribelane. For an in-direct alignment scheme, e.g. a scheme that aligns to another layer than the layer to which overlay is being measured, the number of needed alignment marks can be reduced. Simultaneously there is a requirement to reduce the size of alignment mark sub-segmentations without compromising the alignment and overlay performance. Smaller features within alignment marks can prevent processing issues like erosion, dishing and contamination. However, when the sub-segmentation size within an alignment mark becomes comparable to the critical dimension, and thus smaller than the alignment-illuminating wavelength, polarization effects might start to occur. Polarization effects are a challenge for optical alignment systems to maintain mark detectability. Nevertheless, this paper shows how to actually utilize those effects in order to obtain enhanced alignment and overlay performance to support future technology nodes. Finally, another challenge to be met for new semiconductor product technologies is the ability to align through semi-opaque materials, like for instance new hard-mask materials. Enhancement of alignment signal strength can be reached by adapting to new alignment marks that generate a higher alignment signal. This paper provides a description of an integral alignment solution that meets with these emerging customer application requirements. Complying with these requirements will significantly enhance the flexibility in production strategies while maintaining or improving the alignment and overlay performance. This paper describes the methodology for optimization of the alignment strategy.

Proceedings Article | 10 May 2005 Paper

Flexible alignment mark design applications using a next generation phase grating alignment system

Paul Hinnen, Hyun-Woo Lee, Stefan Keij, Hiroaki Takikawa, Keita Asanuma, Kazutaka Ishigo, Tatsuhiko Higashiki

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.599494

KEYWORDS: Optical alignment, Semiconducting wafers, Sensors, Overlay metrology, Signal processing, Metrology, Optical design, Neodymium, Diffraction, Diffraction gratings

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