With each technology node, overall focus budgets have become increasingly tighter in order to meet the necessary product requirements. The 7nm node has required us to define new opportunities for addressing top contributors to the focus budget. Field curvature in particular has been identified as a key contributor to the intrafield focus budget, contributing around 50%. This paper will introduce two new methodologies for improving field curvature; one a hardware solution and one a software solution.
An optimal mix-match control strategy for EUV and 193i scanners is crucial for the insertion of EUV lithography at 7nm technology node. The systematic differences between these exposure systems introduce additional cross-platform mixmatch overlay errors. In this paper, we quantify the EUV specific contributions to mix-match overlay, and explore the effectiveness of higher-order interfield and intrafield corrections on minimizing the on-product mix-match overlay errors. We also analyze the impact of intra-field sampling plans in terms of model accuracy and adequacy in capturing EUV specific intra-field signatures. Our analysis suggests that more intra-field measurements and appropriate placement of the metrology targets within the field are required to achieve the on-product overlay control goals for N7 HVM.
The NTD (Negative Tone Developer) process has been embraced as a viable alternative to traditionally, more conventional, positive tone develop processes. Advanced technology nodes have necessitated the adopting of NTD processes to achieve such tight design specifications in critical dimensions. Dark field contact layers are prime candidates for NTD processing due to its high imaging contrast. However, reticles used in NTD processes are highly transparent. The transmission rate of those masks can be over 85%. Consequently, lens heating effects result in a non-trivial impact that can limit NTD usability in a high volume mass production environment. At the same time, Source Mask Optimized (SMO) freeform pupils have become popular. This can also result in untoward lens heating effects which are localized in the lens. This can result in a unique drift behavior with each Zernike throughout the exposing of wafers. In this paper, we present our experience and lessons learned from lens heating with NTD processes. The results of this study indicate that lens heating makes impact on drift behavior of each Zernike during exposure while source pupil shape make an impact on the amplitude of Zernike drift. Existing lens models should be finely tuned to establish the correct compensation for drift. Computational modeling for lens heating can be considered as one of these opportunities. Pattern shapes, such as dense and iso pattern, can have different drift behavior during lens heating.
With numerical apertures > 0.4 there will be broad ranges of angles of incidence of light on masks for EUV systems with 4× lens reduction, leading to several undesirable consequences with current MoSi multilayers and tantalum-based absorbers. An option for reducing the range of incident angles is to increase the lens reduction, but this entails small field sizes with standard 6" mask form factors or necessitates the use of larger masks sizes. Small fields lead to a need for stitching or accepting substantially reduced throughput - a problem for a technology already challenged with respect to cost-of-ownership. The implementation of larger mask formats is straightforward but requires considerable investments in new tools for mask making. New absorbers may provide a solution for high-NA EUV lithography at 4× lens reduction, but much R&D is required to demonstrate that this approach will work.
Requirements for ever tightening overlay control are driving improvements in tool set up and matching procedures, APC
processes, and wafer alignment techniques in an attempt to address both systematic and non systematic sources of
overlay error. Thermal processes used in semiconductor manufacturing have been shown to have drastic and
unpredictable impacts on lithography overlay control. Traditional linear alignment can accommodate symmetric and
linearly uniform wafer distortions even if these defects vary in magnitude wafer to wafer. However linear alignment
cannot accommodate asymmetric wafer distortions caused by variations in film stresses and rapid thermal processes.
Overlay improvement techniques such as Corrections per Exposure can be used to compensate for known systematic
errors. However, systematic corrections applied on a lot by lot basis cannot account for variations in wafer to wafer grid
distortions caused by semiconductor processing. With High Order Wafer Alignment, the sample size of wafer alignment
data is significantly increased and modeled to correct for process induced grid distortions. HOWA grid corrections are
calculated and applied for each wafer. Improved wafer to wafer overlay performance was demonstrated.
How HOWA corrections propagate level to level in a typical alignment tree as well as the interaction of mixing and
matching high order wafer alignment with traditional linear alignment used on less overlay critical levels. This
evaluation included the evaluating the impact of overlay offsets added by systematic tool matching corrections, product
specific corrections per exposure and 10 term APC process control.