Fluorescence lifetime imaging is becoming a powerful tool in biology. A charge-domain CMOS Fluorescence Lifetime
Imaging Microscopy (FLIM) chip using a pinned photo diode (PPD) and the pinned storage diode (PSD) with different
depth of potential wells has been previously developed by the authors. However, a transfer gate between PPD and PSD
causes charge transfer noise due to traps at the channel surface. This paper presents a time-resolved CMOS image sensor
with draining only modulation pixels for fluorescence lifetime imaging, which removes the transfer gate between PPD and
PSD. The time windowing is done by draining with a draining gate only, which is attached along the carrier path from
PPD to PSD. This allows us to realize a trapping less charge transfer between PPD and PSD, leading to a very low-noise
time-resolved signal detection. A video-rate CMOS FLIM chip has been fabricated using 0.18μm standard CMOS pinned
diode image sensor process. The pixel consists of a PPD, a PSD, a charge draining gate (TD), a readout transfer gate (TX)
between the PSD and the floating diffusion (FD), a reset transistor and a source follower amplifier transistor. The pixel
array has 200(Row) x 256(Column) pixels and the pixel pitch is 7.5μm. Fundamental characteristics of the implemented
CMOS FLIM chip are measured. The signal intensity of the PSD as a function of the TD gate voltage is also measured.
The ratio of the signal for the TD off to the signal for the TD on is 212 : 1.
A thermal noise calculation model of high-gain switched-capacitor column noise cancellers for CMOS image sensors is presented. In the high-gain noise canceller with a single noise cancelling stage, the reset noise of the readout circuits dominates the noise at high gain. Using the double-stage architecture using a switched-capacitor gain stage and a sample-and-hold stage using two sampling capacitors, the reset noise of the gain stage can be cancelled. The resulting input referred thermal noise power of high-gain double-stage switched-capacitor noise canceller is revealed to be proportional to (g_a/g_s)/GC_L where g_a, G and C_L are the transconductance, gain and output capacitance of the amplifier, respectively, and g_s is the output conductance of an in-pixel source follower. An important contribution of the proposed noise calculation formula is the inclusion of the influence of the transconductance ratio of the amplifier to that of the source follower. For low-noise design, it is important that the transconductance of the amplifier used in the noise canceller is minimized under the condition of meeting the required response time of the switched capacitor amplifier which is inversely proportional to the cutoff angular frequency.
In this paper, we describe the design and implementation of a one-chip camera device for a capsule endoscope. This experimental chip integrates peripheral circuits required for the capsule endoscope and the wireless transmission function based on a data transmission method using human body conduction. The integrated functional blocks include an image array, a timing generator, a clock generator, a voltage regulator, a 10b cyclic A/D converter, and a BPSK modulator. It can be operated autonomously with 3 pins (VDD, GND, and DATAOUT). A prototype chip which has 320x240 effective pixels was fabricated using 0.25μm CMOS image sensor process and the autonomous imaging was demonstrated. The chip size is 4.84mmx4.34mm. With a 2.0 V power supply, the analog part consumes 950µW and the total power consumption at 6 fps (20MHz carrier frequency) is about 3mW.
This paper presents a method of low light imaging using an extremely small capacitor for charge detection in a CMOS image sensor and a high-precision low-noise analog-to-digital converter. A condition for photon counting is that the charge-to-voltage conversion gain is much higher than the root mean square (rms) random noise of the readout circuits. The other condition is that the quantization step of the A/D converter is chosen to be the same as the conversion gain or the amplified conversion gain if the pixel output is further amplified. Simulation results show that if the rms random noise is
reduced to one-sixth of the conversion gain, the 10 times digital integration without the noise increase is possible. This means that even if a very small charge detection capacitor and a relative small power supply voltage are used, a sufficient dynamic range can be achieved by the digital integration without noise increase.
For high-end or low-power CMOS devices, accurate control of the threshold voltage (Vth) is crucial because Vth deviation from the target value decreases the performance and yield of devices. In the conventional process, Vth is determined by channel doping performed early in the fabrication process, and cannot be corrected afterwards even if the variation in the gate length and gate oxide thickness resulting from the fabrication process is large. With the scaling down of devices, accurate control of Vth becomes even more difficult because the effect of the process variation becomes more pronounced. We propose a new feed- forward adjustment scheme for Vth by using post- metallization hydrogen ion implantation. The implanted hydrogen deactivates channel impurities and decreases Vth for both NMOS and PMOSFETs, and this effect remains stable after standard back-end process including post-metallization annealing (400 degrees Celsius). Th Vth change obtained was about 0.1 V at a hydrogen dosage of 1 x 1013 cm-2 for NMOS and PMOS FETs. The impact of this technique on oxide reliability is small and acceptable for practical usage. Using this technique, we can adjust Vth after we measure its actual value and compensate for the Vth variation caused by processing. Hydrogen ion implantation is thus a useful technique for feed-forward yield management.