KEYWORDS: Directed self assembly, Etching, System on a chip, Silicon, Annealing, Scanning electron microscopy, Plasma etching, Line width roughness, Picosecond phenomena, Optical lithography
In this work, we present completely industry adapted processes for high-chi PS-PDMS block copolymers. DSA was performed on trenches fabricated within standard photolithography stacks and pattern transfer was made by using etching processes similar to those used for gate etching in industry. We propose the alignment of two different PS-PDMS (45.5kg/mol, 16kg/mol) solely by thermal annealing. By adding plasticizer molecules in the high molecular weight BCP (45.5k), we have not only avoided solvent vapor annealing but also reduced significantly the processing time. The properties of the guiding lines and the quality of the final BCP hard mask (CD uniformity, LWR, LER) were investigated.
Block CoPolymer (BCP) self-assembly creates periodical patterns with feature sizes eventually below 10 nm. On plain substrates, ordering is only obtained in grains not larger than a few micrometers but self-assembly in trenches of a pattern (using so-called graphoepitaxy technique) can create long-range order between the polymer micro-domains. As a result, such directed self-assembly (DSA) approaches may be used as ultra-high resolution patterning schemes in the microelectronics industry. Due to its ease of processing, a large majority of the lithographic BCP work reported so far concerned polystyreneblock- polymethylmethacrylate (PS-b-PMMA). Researchers show now an increased interest to polystyrene-blockpolydimethylsiloxane (PS-b-PDMS) block copolymers due to its improved resolution. In the present study, typical industry-like photolithography stacks are patterned by combining graphoepitaxy with cylindrical PS-b-PDMS BCP and state of the art plasma etching technologies. The industry like photolithography stack is fabricated on 300 mm diameter silicon wafers, and composed of three layers: Spin-On-Carbon (SOC), Siliconcontaining Anti-Reflective Coating (SiARC) and 193 nm photolithography resist. About 60 nm deep trenches are first patterned by plasma etching in the SiARC/SOC stack using the 193 nm photolithography resist mask. These trenches are then used to confine the BCP and guide the self-assembly of horizontal PDMS cylinders. Wetting conditions allows avoiding the interfacial PDMS wetting layer at the bottom and lateral interfaces after the solvent annealing step. Finally, dedicated pulsed plasma etching conditions were developed in order to reveal the BCP patterns, transfer them into the remaining SOC layer under the trenches and finally into the underlying silicon substrate. 15 nm half-pitch dense line/space features are formed with a height up to 105 nm. In conclusion, long-range order line/space features could be produced by using horizontal cylindrical high Flory- Huggins parameter (χ) BCPs combined with industry-type photolithography stacks.
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