Mr. Staf Verhaegen Profile

Staf Verhaegen

Project Engineer ASIC Design at imec

SPIE Involvement:

Author

Publications (26)

Proceedings Article | 8 April 2011 Paper

Patterning challenges in setting up a 16nm node 6T-SRAM device using EUV lithography

Tom Vandeweyer, Johan De Backer, Janko Versluijs, Vincent Truffert, Staf Verhaegen, Monique Ercken, Mircea Dusa

Proceedings Volume 7969, 79691K (2011) https://doi.org/10.1117/12.881690

KEYWORDS: Optical lithography, Etching, Extreme ultraviolet lithography, Optical proximity correction, Extreme ultraviolet, Lithography, Critical dimension metrology, Photomasks, Semiconducting wafers

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SPIE Journal Paper | 1 January 2011

Experimental verification of source-mask optimization and freeform illumination for 22-nm node static random access memory cells

Joost Bekaert, Bart Laenens, Staf Verhaegen, Lieve Van Look, Darko Trivkovic, Frederic Lazzarino, Geert Vandenberghe, Paul van Adrichem, Robert Socha, Stephen Hsu, Hua-yu Liu, Orion Mouraille, Koen Schreel, Mircea Dusa, Jörg Zimmermann, Paul Gräupner, Jens Neumann

JM3, Vol. 10, Issue 1, 013008, (January 2011) https://doi.org/10.1117/12.10.1117/1.3541778

KEYWORDS: Source mask optimization, Photomasks, Diffractive optical elements, Semiconducting wafers, Scanners, Manufacturing, Double patterning technology, Fiber optic illuminators, Optical lithography, Lithographic illumination

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Proceedings Article | 11 March 2010 Paper

Joint-optimization for SRAM and logic for 28nm node and below

Staf Verhaegen, Michael Smayling, Peter De Bisschop, Bart Laenens

Proceedings Volume 7641, 764107 (2010) https://doi.org/10.1117/12.846595

KEYWORDS: Logic, Lithography, Optical lithography, Double patterning technology, Electroluminescence, Fiber optic illuminators, Transistors, Photomasks, Source mask optimization, Lithium

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Proceedings Article | 4 March 2010 Paper

Freeform illumination sources: an experimental study of source-mask optimization for 22-nm SRAM cells

J. Bekaert, B. Laenens, S. Verhaegen, L. Van Look, D. Trivkovic, F. Lazzarino, G. Vandenberghe, P. van Adrichem, R. Socha, S. Baron, M. C. Tsai, K. Ning, S. Hsu, H. Y. Liu, M. Mulder, A. Bouma, E. van der Heijden, O. Mouraille, K. Schreel, J. Finders, M. Dusa, J. Zimmermann, P. Gräupner, J. T. Neumann, C. Hennerkes

Proceedings Volume 7640, 764008 (2010) https://doi.org/10.1117/12.846918

KEYWORDS: Source mask optimization, Photomasks, Semiconducting wafers, Diffractive optical elements, Manufacturing, Double patterning technology, Scanners, Electroluminescence, Fiber optic illuminators, Optical lithography

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Proceedings Article | 4 March 2010 Paper

Litho-process-litho for 2D 32nm hp Logic and DRAM double patterning

Patrick Wong, Vincent Wiaux, Staf Verhaegen, Nadia Vandenbroeck

Proceedings Volume 7640, 76400I (2010) https://doi.org/10.1117/12.846998

KEYWORDS: Double patterning technology, Thin film coatings, Optical lithography, Logic, Semiconducting wafers, Electroluminescence, Image processing, Line width roughness, Printing, Surface plasmons

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SPIE Journal Paper | 1 July 2009

Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows

Kevin Lucas, Christopher Cork, Alexander Miloslavsky, Gerard Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Gregory Rollins, Vincent Wiaux, Staf Verhaegen

JM3, Vol. 8, Issue 03, 033002, (July 2009) https://doi.org/10.1117/12.10.1117/1.3158061

KEYWORDS: Semiconducting wafers, Double patterning technology, Lithography, Optical lithography, Etching, Photomasks, Optical proximity correction, Metals, Standards development, Critical dimension metrology

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Proceedings Article | 4 December 2008 Paper

A methodology for double patterning compliant split and design

Vincent Wiaux, Staf Verhaegen, Fumio Iwamoto, Mireille Maenhoudt, Takashi Matsuda, Sergei Postnikov, Geert Vandenberghe

Proceedings Volume 7140, 71401X (2008) https://doi.org/10.1117/12.804697

KEYWORDS: Double patterning technology, Optical lithography, Optical proximity correction, Logic, Metals, Photomasks, Etching, Failure analysis, Resolution enhancement technologies, Critical dimension metrology

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Proceedings Article | 17 October 2008 Paper

Printability verification for double-patterning technology

Gerard Luk-Pat, Petrisor Panaite, Kevin Lucas, Christopher Cork, Vincent Wiaux, Staf Verhaegen, Mireille Maenhoudt

Proceedings Volume 7122, 71220Q (2008) https://doi.org/10.1117/12.801545

KEYWORDS: Etching, Lithography, Printing, Double patterning technology, Optical proximity correction, Critical dimension metrology, Resolution enhancement technologies, Scanning electron microscopy, Bridges, Extreme ultraviolet

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Proceedings Article | 1 April 2008 Paper

Split and design guidelines for double patterning

Vincent Wiaux, Staf Verhaegen, Shaunee Cheng, Fumio Iwamoto, Patrick Jaenen, Mireille Maenhoudt, Takashi Matsuda, Sergei Postnikov, Geert Vandenberghe

Proceedings Volume 6924, 692409 (2008) https://doi.org/10.1117/12.774104

KEYWORDS: Double patterning technology, Optical lithography, Logic, Optical proximity correction, Photomasks, Metals, Etching, Failure analysis, Immersion lithography, Image resolution

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Proceedings Article | 20 March 2008 Paper

Interactions of double patterning technology with wafer processing, OPC and design flows

Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Greg Rollins, Vincent Wiaux, Staf Verhaegen

Proceedings Volume 6924, 692403 (2008) https://doi.org/10.1117/12.778267

KEYWORDS: Semiconducting wafers, Optical lithography, Photomasks, Double patterning technology, Lithography, Etching, Metals, Optical proximity correction, 193nm lithography, Standards development

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Proceedings Article | 12 March 2008 Paper

Litho variations and their impact on the electrical yield of a 32nm node 6T SRAM cell

Staf Verhaegen, Stefan Cosemans, Mircea Dusa, Pol Marchal, Axel Nackaerts, Geert Vandenberghe, Wim Dehaene

Proceedings Volume 6925, 69250R (2008) https://doi.org/10.1117/12.773333

KEYWORDS: Transistors, Line width roughness, Critical dimension metrology, Monte Carlo methods, Double patterning technology, Optical lithography, Device simulation, Electroluminescence, Etching, Very large scale integration

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Proceedings Article | 12 March 2008 Paper

Checking design conformance and optimizing manufacturability using automated double patterning decomposition

Chris Cork, Brian Ward, Levi Barnes, Ben Painter, Kevin Lucas, Gerry Luk-Pat, Vincent Wiaux, Staf Verhaegen, Mireille Maenhoudt

Proceedings Volume 6925, 69251Q (2008) https://doi.org/10.1117/12.774647

KEYWORDS: Double patterning technology, Manufacturing, Optical lithography, Photomasks, Logic, Optical proximity correction, Ultraviolet radiation, Lithography, Semiconducting wafers, Phase shifts

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Delays in equipment availability for both Extreme UV and High index immersion have led to a growing interest in double patterning as a suitable solution for the 22nm logic node. Double patterning involves decomposing a layout into two masking layers that are printed and etched separately so as to provide the intrinsic manufacturability of a previous lithography node with the pitch reduction of a more aggressive node. Most 2D designs cannot be blindly shrunk to run automatically on a double patterning process and so a set of guidelines for how to layout for this type of flow is needed by designers. While certain classes of layout can be clearly identified and avoided based on short range interactions, compliance issues can also extend over large areas of the design and are hard to recognize. This means certain design practices should be implemented to provide suitable breaks or performed with layout tools that are double patterning compliance aware. The most striking set of compliance errors result in layout on one of the masks that is at the minimum design space rather than the relaxed space intended. Another equally important class of compliance errors is that related to marginal printability, be it poor wafer overlap and/or poor process window (depth of focus, dose latitude, MEEF, overlay). When decomposing a layout the tool is often presented with multiple options for where to cut the design thereby defining an area of overlap between the different printed layers. While these overlap areas can have markedly different topologies (for instance the overlap may occur on a straight edge or at a right angled corner), quantifying the quality of a given overlap ensures that more robust decomposition solutions can be chosen over less robust solutions. Layouts which cannot be decomposed or which can only be decomposed with poor manufacturability need to be highlighted to the designer, ideally with indications on how best to resolve this issue. This paper uses an internally developed automated double pattern decomposition tool to investigate design compliance and describes a number of classes of non-conforming layout. Tool results then provide help to the designer to achieve robust design compliant layout.

Proceedings Article | 21 March 2007 Paper

Double pattern EDA solutions for 32nm HP and beyond

George Bailey, Alexander Tritchkov, Jea-Woo Park, Le Hong, Vincent Wiaux, Eric Hendrickx, Staf Verhaegen, Peng Xie, Janko Versluijs

Proceedings Volume 6521, 65211K (2007) https://doi.org/10.1117/12.712773

KEYWORDS: Double patterning technology, Photomasks, Optical proximity correction, Optical lithography, Metals, Electronic design automation, Etching, Manufacturing, Logic, Image processing

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The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET). One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an optical extension [1]. The theoretical k₁ for a double-patterning technique of a 32nm half-pitch (HP) design for a 1.35NA 193nm imaging system is 0.44 whereas the k₁ for a single-exposure technique of this same design would be 0.22 [2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and OPC without encountering mask constraints. Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of DP requires the evolution and adoption of design restrictions by specifically tailored design rules. The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a production environment. As with any dual-mask RET application, there are the classical overlay requirements between the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration. For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go beyond this with the coupling of their model-based and process-window applications. This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA solutions were further analyzed and quantified utilizing a verification flow.

Proceedings Article | 21 March 2007 Paper

Double patterning design split implementation and validation for the 32nm node

Martin Drapeau, Vincent Wiaux, Eric Hendrickx, Staf Verhaegen, Takahiro Machida

Proceedings Volume 6521, 652109 (2007) https://doi.org/10.1117/12.712139

KEYWORDS: Double patterning technology, Optical lithography, Process control, Lithography, Logic, Optical proximity correction, Photomasks, Etching, Image processing, Immersion lithography

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Proceedings Article | 21 March 2007 Paper

Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node

Axel Nackaerts, Staf Verhaegen, Mircea Dusa, Hans Kattouw, Frank van Bilsen, Serge Biesemans, Geert Vandenberghe

Proceedings Volume 6521, 65210N (2007) https://doi.org/10.1117/12.713385

KEYWORDS: Transistors, Overlay metrology, Critical dimension metrology, Etching, Lithography, Semiconducting wafers, Statistical analysis, Instrument modeling, Logic

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Proceedings Article | 24 March 2006 Paper

Compensating measured intra-wafer ring oscillator stage delay with intra-wafer exposure dose corrections

Staf Verhaegen, Axel Nackaerts, Mircea Dusa, Rene Carpaij, Geert Vandenberghe, Jo Finders

Proceedings Volume 6152, 61521Y (2006) https://doi.org/10.1117/12.659320

KEYWORDS: Oscillators, Semiconducting wafers, Etching, Critical dimension metrology, Transistors, Picosecond phenomena, Analog electronics, Digital electronics, Scanners, Annealing

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Proceedings Article | 5 May 2005 Paper

Optical extensions integration for a 0.314-µm² 45-nm node 6-transistor SRAM cell

Staf Verhaegen, Axel Nackaerts, Vincent Wiaux, Eric Hendrickx, Geert Vandenberghe

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600862

KEYWORDS: Integrated optics, Lithography, Resolution enhancement technologies, Microelectronics, Manufacturing, Printing, Scanners, Fiber optic illuminators, Lithographic illumination, Double patterning technology

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A target of the 45nm node development at IMEC is to produce a working 6-transistor SRAM (6-T SRAM) cell. Here we describe the lithographic solutions for this challenge. Following the requirements of the ITRS Roadmap requires challenging k₁ values. A classical 6-transistor SRAM design is difficult to scale to lower k1 values for imaging and overlay reasons. In this paper we discuss the litho friendly design that was used to originally produce a working 0.314μm² 45nm node 6-transistor SRAM cell. The design was scaled to a k₁ value of 0.31 for printing the active area layer on a 0.75NA ArF scanner at IMEC. Later on this was further scaled to a k₁ of 0.280 and a cell size of 0.274μm² for a working cell and imaging with a k₁ of 0.265 on a higher NA tool. Various resolution enhancement techniques have been used for the three most critical layers of the SRAM cell: active area, poly gates and contact holes. Although designed unidirectional, the active area and the poly layer of the SRAM cell have critical features in two directions and therefore choosing the right illuminator shape is not straightforward. A pupil shape optimizer was used to maximize the contrast of the aerial image of the various critical features in these layers. For the contact layer the minimal pitch in the design is 160nm, which corresponds to a k₁ of 0.31. The pattern was split up into two images to increase the minimum pitch for the imaging to 190nm. Since off-axis illumination is used to print the 190nm pitch, assist features are added to the more sparse features. Contacts are not placed on a regular rectangular grid and additionally non-square contacts are used for local interconnects. This complicates the placement of the assist features and the interference mapping lithography (IML) technology was used to help in this task. The split design has been used in a double patterning approach in the SRAM process flow. In this paper we show that all the above-mentioned resolution enhancement techniques have been successfully integrated and that it resulted in a working 45nm node SRAM cell.

Proceedings Article | 27 December 2002 Paper

Analysis of the impact of reticle CD variations on the available process windows for a 100-nm CMOS process

Staf Verhaegen, Geert Vandenberghe, Rik Jonckheere, Kurt Ronse

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.467915

KEYWORDS: Reticles, Critical dimension metrology, Semiconducting wafers, Electroluminescence, Photomasks, Optical proximity correction, 3D metrology, Cadmium, Resolution enhancement technologies, Photoresist processing

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Proceedings Article | 16 August 2002 Paper

OPC aware mask and wafer metrology

Wilhelm Maurer, Vincent Wiaux, Rik Jonckheere, Vicky Philipsen, Thomas Hoffmann, Staf Verhaegen, Kurt Ronse, Jonathan England, William Howard

Proceedings Volume 4764, (2002) https://doi.org/10.1117/12.479350

KEYWORDS: Optical proximity correction, Photomasks, Lithography, Metrology, Image processing, Scanning electron microscopy, Semiconducting wafers, Image analysis, Transistors, Line edge roughness

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Proceedings Article | 30 July 2002 Paper

Assessment of OPC effectiveness using two-dimensional metrics

Vincent Wiaux, Vicky Philipsen, Rik Jonckheere, Geert Vandenberghe, Staf Verhaegen, Thomas Hoffmann, Kurt Ronse, William Howard, Wilhelm Maurer, Moshe Preil

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474588

KEYWORDS: Reticles, Optical proximity correction, Photomasks, Scanning electron microscopy, Semiconducting wafers, Critical dimension metrology, Optical lithography, Metrology, Printing, Logic

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A complete evaluation of the optical proximity effects (OPE) and of their corrections (OPC) requires a quantitative description of two-dimensional (2D) parameters, both at resist- and at reticle-level. Because the 2D behaviour at line-ends and at line-corners can become a limiting factor for the yield, it should be taken into account when characterising a process, just as the CD- and pitch-linearity are already kept under control. This implies the measurement of 2D-metrics in a precise way. We used an SEM Image Analysis tool (ProDATA SIAM) to define and measure various OPC-relevant metrics for a C013 process. For the METAL (M1) process, we show that the overlap between line-ends of M1-trenches and underlying nominal contacts is a relevant metric to describe the effectiveness of hammerheads. Moreover, it is an interesting metric to combine with the CD process window. For the GATE process, we demonstrate that for a given set of metrics there is a degree of OPC aggressiveness beyond which it is not worth to go. We considered both line-end shortening (LES) and corner rounding affecting the poly linewidth close to a contact pad, and this on various logic circuits having received different degrees of fragmentation. Finally the knowledge of the actual line-end contour on the reticle allows one to simulate separately the printing effect of that area loss at reticle line-ends. The area loss measured by comparing the extracted contour to the target one is regarded as a combination of pull-back and area loss at corners. For our C013 gate process, and for the 130nm lines at a 1:1.25 duty cycle, those two parameters contribute together to approximetely 40% of the measured LES in the resist. This fact raises the question of specifications on 2D reticle parameters. We also find a linear correlation between the area loss at reticle line-end corners and the corresponding increase of LES on the wafer, which suggests a way towards putting specifications on the reticle line-ends.

Proceedings Article | 11 March 2002 Paper

Challenge for sub-100-nm DRAM gate printing using ArF lithography with combination of moderate OAI and attPSM

Young-Chang Kim, Geert Vandenberghe, Staf Verhaegen, Kurt Ronse

Proceedings Volume 4562, (2002) https://doi.org/10.1117/12.458259

KEYWORDS: Photomasks, Critical dimension metrology, Semiconducting wafers, Monte Carlo methods, Nanoimprint lithography, Printing, Lithography, Resolution enhancement technologies, Binary data, Error analysis

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Proceedings Article | 14 September 2001 Paper

CD control for two-dimensional features in future technology nodes

Staf Verhaegen, Ronald Gordon, Rik Jonckheere, Martin McCallum, Kurt Ronse

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435736

KEYWORDS: Critical dimension metrology, Reticles, Monte Carlo methods, Diffraction, Lithography, Photomasks, Computer simulations, Optical proximity correction, Sodium, Optical lithography

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Proceedings Article | 14 September 2001 Paper

Model-based OPC for first-generation 193-nm lithography

Kevin Lucas, James Word, Geert Vandenberghe, Staf Verhaegen, Rik Jonckheere

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435670

KEYWORDS: Optical proximity correction, Reticles, Model-based design, Semiconducting wafers, Data modeling, 193nm lithography, Lithography, Optical lithography, Scanning electron microscopy, Process modeling

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Proceedings Article | 5 September 2001 Paper

Reticle quality needs for advanced 193-nm lithography

Rik Jonckheere, Geert Vandenberghe, Vincent Wiaux, Staf Verhaegen, Kurt Ronse

Proceedings Volume 4409, (2001) https://doi.org/10.1117/12.438345

KEYWORDS: Photomasks, Optical proximity correction, Reticles, Semiconducting wafers, Printing, 193nm lithography, Critical dimension metrology, Metrology, Lithography, Optical lithography

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Proceedings Article | 5 July 2000 Paper

Limits of optical lithography

Mireille Maenhoudt, Staf Verhaegen, Kurt Ronse, Peter Zandbergen, Edward Muzio

Proceedings Volume 4000, (2000) https://doi.org/10.1117/12.389027

KEYWORDS: Critical dimension metrology, Photomasks, Reticles, Resolution enhancement technologies, 193nm lithography, Monte Carlo methods, Binary data, Lithographic illumination, Optical lithography, Lithography

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Proceedings Article | 26 July 1999 Paper

Feasibility of printing 0.1-um technology with optical lithography

Mireille Maenhoudt, Staf Verhaegen, Kurt Ronse, Donis Flagello, Bernd Geh, Winfried Kaiser

Proceedings Volume 3679, (1999) https://doi.org/10.1117/12.354347

KEYWORDS: Critical dimension metrology, Reticles, Electroluminescence, Printing, Lithography, Lithographic illumination, Photomasks, 193nm lithography, Binary data, Resolution enhancement technologies

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Showing 5 of 26 publications

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