A fully error corrected quantum machine is one of the keys to unlocking the promise and potential of quantum computing. It is now widely accepted that this will require thousands if not millions of identical, highly coherent, interconnected qubits and highlights the increasing need for improving fabrication and scalability of current qubit implementations. Conventional qubit fabrication processes, many relying on lift-off, suffer from low yield and poor uniformity. We outline progress on realizing qubits in a 300 mm fabrication facility with state-of-the-art tooling and advanced process technology and demonstrate advantages of foundry compatible flows for both spin and superconducting qubits.
In this paper proof-of-principle demonstrations of spin-on carbon (SOC)/spin-on glass (SOG)-based lithography processes which could replace standard patterning stacks within the FEOL for upcoming advanced nodes like N10/N7 are presented. At these dimensions the standard lithography approaches that have been utilized within the previous nodes will begin to run into fundamental limitations as a result of the extremely high aspect ratios of the device topography, requiring both new materials as well as new patterning flows in order to allow for continued device scaling. Here, novel SOC/SOG-based patterning flows have been demonstrated which could be applied to implement Source Drain Extension implantations and epitaxial growth processes for CMOS FinFET device architectures even down at N10/N7 dimensions.
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