This paper describes various VLSI systems for microphotonic applications. The first project investigates an optimum phase design implementing a multi phase Opto-ULSI processor for multi-function capable optical networks. This research is oriented around the initial development of an 8 phase Opto-ULSI processor that implements a Beam Steering (BS) Opto-ULSI processor (OUP) for integrated intelligent photonic system (IIPS), while investigating the optimal phase characteristics and developing compensation for the nonlinearity of liquid crystal. The second part provides an insight into realisation of a novel 3-D configurable chip based on "sea-of-pixels" architecture, which is highly suitable for applications in multimedia systems as well as for computation of coefficients for generation of holograms required in optical switches. The paper explores strategies for implementation of distributed primitives for arithmetic processing. This entails optimisation of basic cells that would allow using these primitives as part of a 3-D "sea-of-pixel" configurable processing array. The concept of 3-D Soft-Chip Technology (SCT) entails integration of "Soft-Processing Circuits" with "Soft-Configurable Circuits", which effectively manipulates hardware primitives through vertical integration of control and data. Thus the notion of 3-D Soft-Chip emerges as a new design paradigm for content-rich multimedia, telecommunication and photonic-based networking system applications. Combined with the effective manipulation of configurable hardware arithmetic primitives, highly efficient and powerful soft configurable processing systems can be realized.
Proc. SPIE. 5274, Microelectronics: Design, Technology, and Packaging
KEYWORDS: Semiconductors, Networks, Field programmable gate arrays, Computer programming, Computer simulations, Microelectronics, System integration, System on a chip, Standards development, Information operations
This paper presents the test and validation of FPGA based IP using the concept of remote testing. It demonstrates how a virtual tester environment based on a powerful, networked Integrated Circuit testing facility, aimed to complement the emerging Australian microelectronics based research and development, can be employed to perform the tasks beyond the standard IC test. IC testing in production consists in verifying the tested products and eliminating defective parts. Defects could have a number of different causes, including process defects, process migration and IP design and implementation errors. One of the challenges in semiconductor testing is that while current fault models are used to represent likely faults (stuck-at, delay, etc.) in a global context, they do not account for all possible defects. Research in this field keeps growing but the high cost of ATE is preventing a large community from accessing test and verification equipment to validate innovative IP designs. For these reasons a world class networked IC teletest facility has been established in Australia under the support of the Commonwealth government. The facility is based on a state-of-the-art semiconductor tester operating as a virtual centre spanning Australia and accessible internationally. Through a novel approach the teletest network provides virtual access to the tester on which the DUT has previously been placed. The tester software is then accessible as if the designer is sitting next to the tester. This paper presents the approach used to test and validate FPGA based IPs using this remote test approach.
Mobile multimedia communication has rapidly become a significant area of research and development constantly challenging boundaries on a variety of technological fronts. The processing requirements for the capture, conversion, compression, decompression, enhancement, display, etc. of increasingly higher quality multimedia content places heavy demands even on current ULSI (ultra large scale integration) systems, particularly for mobile applications where area and power are primary considerations. The ADC presented in this paper is designed for a vertically integrated (3D) system comprising two distinct layers bonded together using Indium bump technology. The top layer is a CMOS imaging array containing analogue-to-digital converters, and a buffer memory. The bottom layer takes the form of a configurable array processor (CAP), a highly parallel array of soft programmable processors capable of carrying out complex processing tasks directly on data stored in the top plane. This paper presents a ADC scheme for the image capture plane. The analogue photocurrent or sampled voltage is transferred to the ADC via a column or a column/row bus. In the proposed system, an array of analogue-to-digital converters is distributed, so that a one-bit cell is associated with one sensor. The analogue-to-digital converters are algorithmic current-mode converters. Eight such cells are cascaded to form an 8-bit converter. Additionally, each photo-sensor is equipped with a current memory cell, and multiple conversions are performed with scaled values of the photocurrent for colour processing.
The Australian Commonwealth government recently announced a grant of $4.75 million as part of a $13.5 million program to establish a world class networked IC tele-test facility in Australia. The facility will be based on a state-of-the-art semiconductor tester located at Edith Cowan University in Perth that will operate as a virtual centre spanning Australia. Satellite nodes will be located at the University of Western Australia, Griffith University, Macquarie University, Victoria University and the University of Adelaide. The facility will provide vital equipment to take Australia to the frontier of critically important and expanding fields in microelectronics research and development. The tele-test network will provide state of the art environment for the electronics and microelectronics research and the industry community around Australia to test and prototype Very Large Scale Integrated (VLSI) circuits and other System On a Chip (SOC) devices, prior to moving to the manufacturing stage. Such testing is absolutely essential to ensure that the device performs to specification. This paper presents the current context in which the testing facility is being established, the methodologies behind the integration of design and test strategies and the target shape of the tele-testing Facility.
Camera-on-a-CMOS chip will be an inevitable component of future intelligent vision systems. However, up till now, the dominant format of data in imaging devices is still analog. The analog photocurrent or sampled voltage is transferred to the ADC via a column or a column/row bus. Moreover, in the active pixel configuration the area occupied by circuitry reduces significantly the fill factor, so that there are heavy constraints imposed on the size of the circuits used. In this paper a concept of back illuminated focal plane is presented. The system consists of two chips bonded face to face using Indium bumps. The top chip, which is the seeing chip, is thinned and the light signal is applied to the bottom surface. The bottom chip is the processing chip and it contains a distributed array of analog-to digital converters. As the seeing chip is fully dedicated to photosensors the fill factor can be increased from 25-40% possible on a single plane to over 95% with two planes. The analog-to-digital converters are algorithmic current-mode converters, where one-bit cell is implemented in the processing area facing one-pixel. Eight such cells are cascaded to form an 8-bit converter. As a result, a fully digital pixel readout is obtained.
Proc. SPIE. 3893, Design, Characterization, and Packaging for MEMS and Microelectronics
KEYWORDS: Logic, Switching, Gallium arsenide, Microelectronics, Very large scale integration, Transistors, Integrated circuits, Field effect transistors, Digital electronic circuits, Digital electronics
There are numerous sources of noise present in the VLSI integrated circuits. A function that can measure the ability of a digital logic circuit to operate error-free in a noisy environment is noise margin which can be define in several ways from the transfer characteristic of the logic circuit. It is critical to be able to precisely evaluate a noise margin for Gallium Arsenide circuits, as its value is usually limited to the extent that only NOR gates are allowed in DCFL digital circuits and NAND gates, where stacked pull down transistors would be required, are excluded. In the paper, the best-case and worst-case static noise margin are discussed and it is shown that not only the load but also the noise voltage has to be included when evaluating a transfer function. Fortunately, the best-case noise margin can still be calculated with the nose free transfer function. But the more useful worst-case noise margin is shown to depend on the transfer function including the noise source. Therefore, as was already pointed out by Lohstroh for CMOS circuits, the best way to calculate the noise margin is to start a quasi-static transient simulation with all noise sources being zero and by increasing the amplitudes of the noise sources slowly compared to the switching speed of the logic circuits. The worst-case noise margin is then found as the noise amplitude at which the chain exhibits a malfunction. Since an infinitely long chain is sown to be equivalent to a flip-flop the flip-flop can be used for the simulation instead. The examples of an inverter and an AND gate illustrate the theory presented.
There are many applications where ultra-fast digital arithmetic circuits are required. At ultra-high speeds a considerable part of power is dissipated within a clock generation and distribution syste. At the same time, at gigahertz frequencies the clock skew becomes a factor limiting the speed of the system. This paper presents a design methodology for highly pipelined, self-timed circuits and systems suitable for multimedia applications using Gallium Arsenide MESFET as the base technology implementation of latched logic design style (PDLL, LCFL). The use of latched logic together with the absence of the global clock provides for low power dissipation while maintaining very high speed of the system. The main advantage of the latched structure is provided by the feedback which ensures that the nose margin is higher than for a simple Direct Coupled FET Logic gate. This enables to use serial connections of the E-type transistors in the pull-down section. Therefore, in GaAs latched logic it is possible to implement logic gates based on the AND function which have several control inputs and that they generate at least one control signal for handshaking. For the typical 4- phase handshaking protocol the input signals are enable and start and the required generated signal is Done. In the paper the appropriate modifications of the handshaking protocol to accommodate the properties of the latched logic GaAs circuits is presented an the inherent latching property of LCFL is exploited to eliminate latches separate from the logic blocks in the classic pipeline. Several circuit examples demonstrate the advantages of the proposed circuit techniques.