Mapper has installed its first product, the FLX–1200, at CEA-Leti in Grenoble (France). This is a maskless lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. The FLX-1200, containing 65,000 parallel electron beams, has a 1 wph throughput at 300 mm wafers and is capable of patterning any resolution and any different type of structure all the way down to 28 nm node patterns. The system has an optical alignment system enabling mix-and-match with optical 193 nm immersion system using standard NVSM marks. Mapper Lithography and CEA-Leti are collaborating to develop turnkey solution for specific applications.
In figure 1 the basic operation principle of the Mapper technology is shown. The electron optics have no central crossovers making them intrinsically insensitive to Coulomb forces (electron repulsion). The electron optics are modular and much cheaper than high-NA DUV optics, and can be replaced or upgraded in the field. The wafer exposure happens one column of fields at a time and always in the same direction. There is no need to meander. The focus and leveling is performed during stage fly-back to reduce metrology overhead. Each column of fields is aligned separately, with dedicated alignment targets.
Figure 1, Basic operation of the Mapper technology.
In figure 2 the way the beams are distributed over the electron optics slit is shown. The writing strategy is as follows:
- There are up to 5 slits, staggered in X direction for reasons of wafer coverage. The approach is roughly analogous to an inkjet printer
- Each slit area consists of 204 x 13 individual groups of beamlets, organized in a hexagonal array.
- All beamlets are simultaneously horizontally deflected over a range of 2µm while the wafer is scanned vertically.
- Each group comprises 49 individual beamlets (7x7). Each of the 49 beamlets can independently be switched on and off during exposure.
- Each beamlet results in a Gaussian spot on the wafer with 25 nm FW50 diameter (10.6nm 1).
- Total beamlet count will therefore equal 5 x 204x13 x 49 = 649,740. In the FLX-1200 and FLX-1300 the central 10% are used (one half slit area): 65,000
A more detailed description of the principles of operation is given in [2].
Figure 2,Distribution of the beams over the electron optics slit.
The focus of presentation will be the reporting of the performance achieved of the tool installed at CEA-Leti during endurance runs in full tool configuration. This includes status of:
- Exposure throughput
- Achieved resolution and CD uniformity
- Stitching performance
- Matched Machine Overlay
- Tool availability and uptime
Also the different application areas for such a maskless system are discussed.
In figure 3 a preview of a CD uniformity measurement result is shown. On a 300 mm wafer fields of 5mm x 5mm have been exposed containing 60nm dense lines and spaces. The main source of CD variation is caused by differences between the groups of beamlets. To measure this variation we have taken 824 SEM images, each taken of a pattern written by a different beam group. The result is shown in figure 3. The variation is 8nm 3s, and follows a Gaussian distribution of 6nm 3s.
Figure 3, Distribution of 824 CD measurements results on 60nm dense lines and spaces
Operating maskless, massively parallel electron beam direct write (MEBDW) is an attractive alternative to optical lithography in micro and nano device manufacturing. Mapper Lithography develops MEBDW tools able to pattern wafers, for application nodes down to 28nm, with a throughput around one wafer per hour. A prototype tool from this series, named FLX-1200, is installed in the CEA-Leti clean room. This paper reviews the current performances of this prototype and the methodology used to measure them. On standardized exposure, consisting of 100 fields of 5×5mm2 exposed, in less than one hour, on 300mm silicon wafers, we obtained CD uniformity below 10nm (3σ) and LWR of 4.5nm for 60nm half pitch dense lines. We also demonstrate capability of 15nm and 25nm (3σ) for stitching and overlay errors respectively.
Multiple electron beam direct write lithography is an emerging technology promising to address new markets, such as truly unique chips for security applications. The tool under consideration, the Mapper FLX-1200, exposes long 2.2 μm-wide zones called stripes by groups of 49 beams. The critical dimensions inside and the registration errors between the stripes, called stitching, are controlled by internal tool metrology. Additionally, there is great need for on-wafer metrology of critical dimension and stitching to monitor Mapper tool performance and validate the internal metrology.
Optical Critical Dimension (OCD) metrology is a workhorse technique for various semiconductor manufacturing tools, such as deposition, etching, chemical-mechanical polishing and lithography machines. Previous works have shown the feasibility to measure the critical dimension of non-uniform targets by introducing an effective CD and shown that the non-uniformity can be quantified by a machine learning approach. This paper seeks to extend the previous work and presents a preliminary feasibility study to monitor stitching errors by measuring on a scatterometry tool with multiple optical channels.
A wafer with OCD targets that mimic the various lithographic errors typical to the Mapper technology was created by variable shaped beam (VSB) e-beam lithography. The lithography process has been carefully tuned to minimize optically active systematic errors such as critical dimension gradients. The OCD targets contain horizontal and vertical gratings with a pitch of 100 nm and a nominal CD of 50 nm, and contain various stitching error types such as displacement in X, Y and diagonal gratings.
Sensitivity to all stitching types has been shown. The DX targets showed non-linearity with respect to error size and typically were a factor of 3 less sensitive than the promising performance of DY targets. A similar performance difference has seen in nominally identical diagonal gratings exposed with vertical and horizontal lines, suggesting that OCD metrology for DX cannot be fully characterized due to lithography errors in gratings with vertical lines.
KEYWORDS: Overlay metrology, Metrology, Electron beam lithography, Lenses, Distance measurement, Electron beams, Raster graphics, Semiconducting wafers, Time metrology, Process control
One of the metrology challenges for massively parallel electron beams is to verify that all the beams that are used perform within specification. The Mapper FLX-1200 platform exposes fields horizontally segmented in 2.2 μm-wide stripes. This yields two parameters of interest: overlay is the registration error with respect to a previous layer, and stitching is the registration error between the stripes. This paper presents five novel overlay targets and one novel stitching target tailored for Mapper’s needs and measured on KLA-Tencor Archer 600 image based overlay (IBO) platform. The targets have been screened by exposure of a variable shaped electron beam lithography machine (Vistec VSB 3054 DW) on two different stacks: resist-to-resist and resist-to-etched silicon, both as a trilayer stack. These marks attain a total measurement uncertainty (TMU) down to 0.3 nm and move-and-measure (MAM) time down to 0.3 seconds for both stacks. The stitching targets have an effective TMU of 0.4 nm and a MAM time of 0.75 seconds. In a follow up experiment, the two best performing overlay targets have been incorporated in an exposure by a Mapper FLX-1200. With the new stack a TMU of 0.3 nm and MAM time of 0.35 s have been attained. For 107 out of 140 selected stripes the slope was constant within 2.5%, the offset smaller than 0.5 nm and correlation coefficient R2 > 0.98.
Mapper has installed its first product, the FLX–1200, at CEA-Leti in Grenoble (France). This is a maskless lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. The FLX-1200, containing 65,000 parallel electron beams in a 13mm x 2mm electron optics slit, is capable of patterning any resolution and any different type of structure all the way down to 28 nm node patterns. As of August 2017 the FLX-1200 has a fully operational electron optics column, including a 65,000 beam blanker. In this paper the latest technical achievements of the FLX-1200 have been described: beam current is at 80% of FLX-1300 target (85 minutes per wafer). For 42nm hp dense lines a CDu of 8nm 3σ and a LWR of 5nm 3σ has been demonstrated. The stitching error is 12nm μ+3σ and regarding overlay a 15nm capability demonstrated, provided matching strategy is implemented and the mirror map is calibrated.
KEYWORDS: Etching, Semiconducting wafers, Lithography, Scanning electron microscopy, System on a chip, Optical alignment, Electron beam lithography, Metals, Back end of line, Copper
The maskless electron beam lithography system, based on massively parallel electron-beam writing strategy has the ability for low-cost production of truly unique individual chips in volume manufacturing, compatible with optical systems. Mapper Lithography has introduced the FLX-1200 platform installed at CEA-Leti. This paper will present fully process-integration stepwise developments to be compliant with the single via layer demanding targets based on dual damascene process:
The lithographic performances and etch transfer optimization were firstly evaluated on a layer stack representative of N40 CMOS technology by developing step-by-step approach:
- 1/ Trilayer lithography of via layer and partial etch into low-k development with VSB 50kV
- 2/ Litho/etch process of product wafer with VSB 50keV
- 3/ Trilayer lithography of via pattern and etch into low-k for FLX-1200 multi-beam 5kV
- 4/ last litho of via pattern on product wafer using FLX (no etch yet). In addition, the overlay and CDU capability of FLX-1200 are assessed for via 3, and the alignment to product wafer is tested.
Via patterning integration showing the up-to-date achievements is mature enough to start first customer demos for security application.
Fabrication processes that microelectronic developed for Integrated circuit (IC) technologies for decades, do not meet the new emerging structuration’s requirements, in particular non-IC related technologies one, such as MEMS/NEMS, Micro-Fluidics, photovoltaics, lenses. Actually complex 3D structuration requires complex lithography patterning approaches such as gray-scale electron beam lithography, laser ablation, focused ion beam lithography, two photon polymerization. It is now challenging to find cheaper and easiest technique to achieve 3D structures.
In this work, we propose a straightforward process to realize 3D structuration, intended for silicon based materials (Si, SiN, SiOCH). This structuration technique is based on nano-imprint lithography (NIL), ion implantation and selective wet etching. In a first step a pattern is performed by lithography on a substrate, then ion implantation is realized through a resist mask in order to create localized modifications in the material, thus the pattern is transferred into the subjacent layer. Finally, after the resist stripping, a selective wet etching is carried out to remove selectively the modified material regarding the non-modified one.
In this paper, we will first present results achieved with simple 2D line array pattern processed either on Silicon or SiOCH samples. This step have been carried out to demonstrate the feasibility of this new structuration process. SEM pictures reveals that “infinite” selectivity between the implanted areas versus the non-implanted one could be achieved. We will show that a key combination between the type of implanted ion species and wet etching chemistries is required to obtain such results.
The mechanisms understanding involved during both implantation and wet etching processes will also be presented through fine characterizations with Photoluminescence, Raman and Secondary Ion Mass Spectrometry (SIMS) for silicon samples, and ellipso-porosimetry and Fourier Transform InfraRed spectroscopy (FTIR) for SiOCH samples. Finally the benefit of this new patterning approach will be presented on 3D patterns structures.
In this paper the rules-based correction strategies for the nanoimprint lithography (NIL) technology are addressed using complete Scanning Electron Microscopy (SEM) characterizations. Performed onto 200 mm wafers imprinted with the HERCULES NIL equipment platform, Critical Dimension (CD) uniformity analyses are used to measure the evolution of lines and spaces features dimensions from the master to 50 consecutive imprints. The work brings focus on sub micrometer resolution features with duty cycles from 3 to 7. The silicon masters were manufactured with 193 optical lithography and dry etching and were fully characterized prior to the imprint process. Repeatability tests were performed over 50 wafers for two different processes to collect statistical and comparative data. The data revealed that the CD evolutions can be modelled by quadratic functions with respect to the number of imprints and feature dimension (CD and pitch) on the master. These models are used to establish the rules-based corrections for lines arrays in the scope of nanoimprint master manufacturing, and it opens the discussion on the process monitoring through metrology for the nanoimprint soft stamp technologies.
In this paper a first Critical Dimension (CD) uniformity assessment onto 200 mm wafers printed with the SmartNILTM technology available in the HERCULES® NIL equipment platform is proposed. The work brings focus on sub micrometer resolution features with a depth between 220 and 433 nm. The silicon masters were manufactured with 193 optical lithography and dry etching. A complete Scanning Electron Microscopy (SEM) characterizations were performed over the full masters surface prior to the imprint process. Repeatability tests were performed over 25 wafers first and then on 100 wafers to collect statistics and the CD distribution within a wafer and also wafer to wafer. The data revealed that the CD is evolving imprint after imprint and an explanation based on polymer shrinkage is proposed.
Colour filters using two-dimensional sub wavelength double-breasted rectangular hole, with a 250 nm period, were
proposed and manufactured. Using low-cost, wafer scale thermal NanoImprint lithography, a thin metallic aluminium
silicon alloy layer was patterned into two dimensional structures onto 200 mm wafer size. Process flow proposed in this
paper is fully compatible with IC manufacturing line. A fine tuning of the manufactured design was proposed with arm
widths ranging from 30 nm up to 60 nm, and arm lengths ranging from 100 nm up to 240 nm, keeping the period
constant at 250 nm. Sub 20 nm resolution 200 mm silicon stamp, with aspect ratio larger than 5 were manufactured using
electron beam lithography with proximity correction exposure strategy based on shape modification of the initial design.
At the end 864 different patterns were manufactured and etched in thin 40 nm thick aluminium layer. The sub 30 nm
resolution metallic patterns were then transfer from silicon wafer to transparent glass wafer to perform optical
characterizations. Morphological characterizations and optical measurements of transmission spectra revealed that the
optical response were very sensitive to the fine shape of the patterns etched in the metallic layer.
As we are moving towards sub-32nm node, the question of lithography cost will play a key role with the introduction for
example of Double Patterning. The Nanoimprint lithography is one potential candidate that could become competitive.
Indeed, such technique is very promising and has already proven its ability of being potentially compatible with high
volume manufacturing at low cost in order to make advanced devices. To transfer such ability in a real industrial
environment, progresses have to be done to manufacture high resolution and accurate molds. To overcome this issue,
fine topological characterizations of both coated mold with anti-sticking layer and imprinted materials have to be
performed. Fabricated patterns have to be very well controlled in term of geometry quality, uniformity on the whole
wafer. Moreover, the defectivity of the imprint process must be understood and well controlled to introduce such
lithography process into the industrial environment.
In this paper, we will present some experiments that have been carried out with the 3D-AFM technology on Nanoimprint
molds and various imprinted wafers in order to understand more deeply either the advantages or drawbacks of this
emerging lithography technique. For instance we will discuss about the anti-sticking layer which must be applied on
mold before any imprint in order to keep reliable as much as possible the final industrial process. We will also present
experimental results realized for both UV-NIL and Hot-Embossing NIL which are two different candidates depending on
the final application. In a third part we will show and discuss some experimental results related to the Nanoimprint
defectivity main drawback through the study of capillarity bridges growing.
We report on the use of two original techniques for the quality evaluation of nanoimprint lithography with 50
nm feature size: sub-wavelength blazed diffraction gratings and photoacoustic metrology. Sub-wavelength diffraction
has been used to characterise nanoscale structures by studying the diffraction patterns of visible wavelengths of light
from gratings which are made up of features below the diffraction limit. Diffraction efficiencies of the diffracted orders
are related to the nanoscale line-widths, heights and defects of the gratings. A stamp of a sub-wavelength blazed grating
was fabricated by electron beam lithography and reactive ion etching in silicon and imprinted by NIL with different
tools. Measured diffraction efficiencies agree with those from finite difference time domain simulations and we
demonstrated the possibility to distinguish diffraction patterns from successfully imprinted gratings and those with a
defect. The photoacoustic method has been used for the first time to study nanoimprint polymers. Signals were obtained
from the top and bottom interfaces of polymer layers with aluminium and silicon, respectively, and thicknesses
calculated from the time of flight of the acoustic wave and modelling physical parameters of the polymers, agree well
with those measured by profilometry.
It is well admitted that NanoImprint is a powerfull next generation lithography. Nevertheless many defects may appear during a NanoImprint process. Some of them are clearly related to the stamp or polymer surface properties, or the stamp pattern symmetry breakdown. This paper will address the defectivity issue in imprint process and specially in non printed areas where resist features may appear. They are related to capillary forces between the stamp surface and the polymer. The understanding of their growth with respect to mold-polymer distance and printing process is presented. A specific stamp, with cavity depths ranging from 12-224 nm, has been designed to control the capillary bridge growth. The resulting capillary bridges were characterized as a function of the cavity depth, printing temperature, resist thickness and printing time. Results show that capillary bridge number is strongly influenced by cavity depth and in a less extent by temperature and printing time.
Hot embossing throughput is a key issue, which has been addressed in this paper. We show how it is possible to remove
the mold from the imprinted resist at the imprint temperature. We study reflow behavior of imprinted patterns, and
make a cooling and quenching simulation. This work can lead to design of cooling tools adapted to a given application,
and suits as well for the full wafer imprint, as well for the roll imprint.
Sub 100 nm resolution on 200 mm silicon stamp have been hot embossed into commercial Sumitomo NEB 22 resist. A single dot pattern, exposed with electron beam lithography, has been considered to define the stamp and make thus possible to point out the impact of stamp design onto the printing. Moreover, more complex shapes (triangular, elliptic, random...) with sub 200 nm resolution with and without uniform surrounding frame have been also designed. A large scale of initial resist thickness, from 56 nm to 506 nm, has been printed to assess the effect of polymer flow properties onto the stamp cavities filling and the printed defects. The impact of the pattern symmetry breakdown onto defect generation is clearly shown in this paper in the printed areas as well as in the unprinted areas.
Nanoimprint Lithography (NIL) is a fast, high resolution replication technology for micromechanics, microbiology and even for microelectronic applications in the sub-100nm range. The technique has been demonstrated to be a very promising next generation technique for large-area structure replication up to wafer-level in the micrometer and nanometer scale. For producing nanometer structures the capital investments required are much lower compared to other next generation methods (e-beam writing, x-ray lithography, EUV lithography, ...). Nanoimprint Lithography is based on two different techniques: Hot Embossing (HE) and UV-Nanoimprint Lithography (UV-NIL). Both methods can be used for replicating dense and isolated features in the range of 70nm to 100μm simultaneously on up to 200mm wafers.
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