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The advanced image based M3D inverse lithography technology (ILT) is used to perform full chip mask correction on the Via layer of a 3D-NAND device. 3D NAND devices contain highly repetitive cell and page buffer patterns. To ensure the full chip device performance, the consistency of the mask correction is important. Our strategy is to use the computationally intensive mask optimization solution from the new advanced image based M3D inverse technology to generate a freeform mask which gives the best lithography performance. We then use Tachyon’s Pattern Recognition and Optimization (PRO) engine to propagate the freeform mask solution of the repetitive patterns to the full chip. The periphery of the chip is optimized using conventional OPC methods. The simulation results from the advanced image based M3D inverse technology are compared against the baseline flow, which uses a standard inverse solution. The simulation results from both the flows are further validated on wafer. Significant improvement in overlapping process window (OPW) and CD uniformity is observed using the new advanced inverse technology. The simulation data shows a 32% improvement in depth of focus (DOF), a 5% improvement in the image log slope (ILS) and a 25% reduction in best focus shift (BFS) range. The improvement has also been verified at the wafer-level.
Efficient full-chip SRAF placement using machine learning for best accuracy and improved consistency
Rule-based methods, used since the 90 nm node, require long development time and struggle to achieve good process window performance for complex patterns. Heuristically driven, their development is often iterative and involves significant engineering time from multiple disciplines (Litho, OPC and DTCO).
Model-based approaches have been widely adopted since the 20 nm node. While the development of model-driven placement methods is relatively straightforward, they often become computationally expensive when high accuracy is required. Furthermore these methods tend to yield less consistent SRAFs due to the nature of the approach: they rely on a model which is sensitive to the pattern placement on the native simulation grid, and can be impacted by such related grid dependency effects. Those undesirable effects tend to become stronger when more iterations or complexity are needed in the algorithm to achieve required accuracy.
ASML Brion has developed a new SRAF placement technique on the Tachyon platform that is assisted by machine learning and significantly improves the accuracy of full chip SRAF placement while keeping consistency and runtime under control. A Deep Convolutional Neural Network (DCNN) is trained using the target wafer layout and corresponding Continuous Transmission Mask (CTM) images. These CTM images have been fully optimized using the Tachyon inverse mask optimization engine. The neural network generated SRAF guidance map is then used to place SRAF on full-chip. This is different from our existing full-chip MB-SRAF approach which utilizes a SRAF guidance map (SGM) of mask sensitivity to improve the contrast of optical image at the target pattern edges.
In this paper, we demonstrate that machine learning assisted SRAF placement can achieve a superior process window compared to the SGM model-based SRAF method, while keeping the full-chip runtime affordable, and maintain consistency of SRAF placement . We describe the current status of this machine learning assisted SRAF technique and demonstrate its application to full chip mask synthesis and discuss how it can extend the computational lithography roadmap.
Specifically, in this work we will demonstrate “design intent” optimization for critical BEOL layers using design tolerance bands to guide the source mask co-optimization. The design tolerance bands can be either supplied as part of the original design or derived from some basic rules. Additionally, the EUV stochastic behavior is mitigated by enhancing the image log slope (ILS) for specific key features as part of the overall optimization. We will show the benefit of the “design intent approach” on both bidirectional and unidirectional 28nm min pitch standard logic layouts and compare the more typical iterative SMO approach. Thus demonstrating the benefit of allowing the design to float within the specified range. Lastly, we discuss how the evolution of this approach could lead to layout optimization based entirely on some minimal set of functional requirements and process constraints.
In this study, the authors focus on the increase in image contrast that Source Mask Optimization (SMO) and Optical Proximity Correction (OPC) models deliver when comparing 300 fm and 200 fm light source E95% bandwidth. Using test constructs that follow current N7 / N5 ground rules and multiple pattern deconstruction rules, improvements in exposure latitude (EL), critical dimension (CD) and mask error enhancement factor (MEEF) performance are observed when SMO and OPC are optimized for 200 fm light source bandwidth when compared with the standard 300 fm bandwidth. New SMO-OPC flows will be proposed that users can follow to maximize process benefit. The predicted responses will be compared with the experimental on wafer responses of 7 nm features to lower light source bandwidth.
Recent improvements in bandwidth control have been realized in the XLR platform with Cymer’s DynaPulseTM control technology. This reduction in bandwidth variation translates in the further reduction of CD variation in device structures 5,6. The Authors will review the methodology for determining the impact that bandwidth variation has on CD dose, focus, pitch and bandwidth, which is required to build a dynamic model. This assists in understanding the impact that bandwidth variability has on the accuracy of the Source and Mask optimization and the overall OPC model, which is reviewed and demonstrated.
Full-chip manufacturing reliability check implementation for 90-nm and 65-nm nodes using CPL and DDL
This course provides attendees with a basic working knowledge of the fundamentals and implementation principles of what industry calls with a generic name "double patterning” but in reality it is a multi-patterning technology. This course will tackle the interdisciplinary characteristics of the multipatterning processes examining several pitch division techniques, from double to triple, quadruple or even more split steps, with focus on the key technology components, such as, but not limited to, (a) resolution and lithography options, (b) layout, ground rules and split compliance, (c) process and material, that are combined to create an electrically functional device layer from multiple patterning steps. We will discuss single to multiple patterning pitch-split practical implementations adding complementary and combinatorial techniques based on pitch-divided gratings connected with a cut and/or a block masking layer.
The course presents the lithographic and patterning alternatives of various pitch-split techniques, for example, LithoEtch, LEn where n≥2 and multiple SelfAligned spacer film depositions, like SADP and SAQP. It will underline the interactions between layout style, split compliance, layer polarity, feature bias defined by split process characteristics and will draw attention to the constraints to integrate the pitch-split patterning steps into a complete CMOS process flow. In addition, the course provides information on the materials and material combinations used in multiple patterning processes illustrated by recent industry developments to increase the structural robustness of pitch divided high aspect ratio features and the anti-spacer / cut mask-less approach.
Special attention is given to the unique characteristics of multiple patterning metrology and process control, in particular to model overlay effects into comprehensive CDU budgets supporting the tight process tolerances of the scaling nodes. The course examines the CDU and overlay budget contributors and defines basic requirements for metrology tools performances to support multipatterning.
We will illustrate multipatterning utilization on today’s 3D transistors architecture, FinFet and Nanowires, applied on FEOL and BEOL layers, with unidirectional gratings and cuts or blocks that are needed to create the 2D layout intent. The course offers comprehensive analysis of the combinatorial multiple patterning flows, LE^n, SADP, SAQP with associated cut or block masking layers based on the new Edge Placement Error, EPE, metric, assessing pattern quality for manufacturability. Practical and useful examples from critical device layers of memory and logic devices are included throughout, with particular consideration on how multiple splits operate on device sequential layers using computational lithography optimized splits. The course includes extensive references of relevant publications on double/ multiple patterning processes.
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