EUV lithography has been well-established over the past few years, to be the next technological milestone, to achieve lower pattern resolutions i.e. higher technology nodes. Ensuring a lower defect count however is particularly important for its use in mass-production, because of the considerably high cost of EUV masks. EUV wavelength (actinic EUV inspection) is necessary to be able to catch and characterize EUV defects correctly, particularly phase defects, originating due to imperfections in multi-layers. Defects on a patterned mask require EUV wavelengths (higher resolution) for accurate assessment of their CD impact. However, DUV optics are also employed by mask shops, along with SEM review, as a cost-effective option. Emphasizing the importance of defect handling in EUV masks, especially for EUV masks without pellicles in the memory industry, the most difficult part of EUV mask management is in controlling adder. Detecting smaller adder size is required as mask pattern size is getting smaller in higher technology nodes, which accompanies increased sensitivity of patterned mask inspection and unavoidable increase in noise signal that makes it hard to proper classify mask defects. This paper talks about the details of how DUV inspection optics are utilized to achieve an efficient pre-filtering of EUV mask defects. This, coupled with well-tested automatic defect classification algorithms of Calibre® DefectClassify, results in a reliable solution to manage regular classification of mask defects as real or false, under such sensitive conditions.
The growing adaptation of complex curvilinear masks (CL masks) and Inverse Lithography Technology (ILT) designs for advanced nodes, enabled by Multi-Beam Mask Writer’s ability to effectively write these intricate patterns, has driven the industry to explore Multigons for efficient curvilinear data representation and processing. To enable the industry to evaluate the feasibility of Multigon-based flows, the curvilinear Multigon representation was developed and integrated as an extension to the SEMI P39 OASIS format by the SEMI task force working group. Previous studies have underscored the importance of developing native Multigon processing algorithms to enhance the accuracy and efficiency of curvilinear post-tape-out applications such as Optical Proximity Correction (OPC), Mask Process Correction (MPC), Mask Data Preparation (MDP). Mask Rule Checks (MRCs) serve as a critical verification step to ensure design integrity and manufacturability of curvilinear masks. However, curvilinear masks can be more challenging to verify as they often involve freeform shapes, higher data complexity and large file sizes. In this paper, we will introduce native Multigon-based curvilinear mask rule checks and present a comprehensive study assessing the effectiveness of these checks in scenarios involving Multigon to Multigon and Multigon to Piecewise-Linear (PWL) checks. Furthermore, we will study the runtime of Multigon-based CLMRC and compare the performance to equivalent PWL based checks.
With the advent of advanced nodes, curvilinear mask processing is becoming the convention. Adopting complex curvilinear shapes for modern photomasks using ILT (Inverse Lithography Technique) may aid the pattern fidelity of complex designs. The curvilinear working group has convened on the addition of the MULTIGON record to the OASIS format. MULTIGON is accepted as a preliminary standard in OASIS format for the exploration of new flows and their advantages. Multibeam mask writers are becoming the standard solution at advanced nodes due to their constant write time and ability to pattern complex designs. Multibeam fracture will be pivotal in the MULTIGON based data preparation flows. In this paper, we demonstrate the readiness of Calibre multibeam fracture tools to accept MULTIGON input and generate fractured data to machine format. Existing multibeam mask writers expect Piecewise-Linear (PWL) data as input to their data path. This paper explores two different quantitative methodologies for conversion of MULTIGON input in fracture to Piecewise-Linear output, enabled by the Calibre Mask Data Preparation tools supporting multibeam fracturing. We investigate the impact of these two methodologies: edge-length based and deviation-tolerance based, while processing MULTIGON inputs, and their impact on mask contour quality. We also analyze the impact of the different sampling methods and their sampling values on the mask contour using a nominal EUV mask process model and present results related to these experiments. Consequently, we aim to deduce the acceptable sampling methods and their limits while respecting the sampling frequency described by the mask data preparation process.
The rapidly increasing complexity of photomasks arising from free-form curvilinear mask shapes generated by Inverse Lithography Technology (ILT) has called for exploration of efficient and accurate native curvilinear data representation methodologies. The curvilinear Multigon extension to SEMI P39 OASIS format has been approved as a preliminary standard for the industry to evaluate Multigon-based post-tape-out data preparation flows. In this paper, we will present perspectives on opportunities, challenges, and applications of Multigon-based curvilinear data handling and representation. The representation of a closed curvilinear shape using multiple explicit or implicit Piecewise-Bèzier (PWB) curves will be described, including considerations for ensuring continuity of curves between neighboring Bèziers. A description of useful Multigon properties will be provided, which enables the development of operations fundamental to Computational Lithography, thereby enabling ‘native’ Multigon-based flows. PiecewiseBèzier to Piecewise-Linear (PWL) sampling methods (based on specified quantitative constraints) will be presented as an approach to convert PWB data to edge-based polygon representation such that PWB-based tools can be integrated and tested even in flows where certain components require operations on PWL data. Further, potential approaches, benefits and challenges related to development of Multigon-based data preparation flows will be discussed in the context of Optical Proximity Correction (OPC), Mask Process Correction (MPC) and multibeam mask writer data preparation. Finally, initial results on demonstrating curvilinear MRC (Mask-Rule-Check) on PWB data will be presented.
Each day, semiconductor manufacturing companies (fabs) run distributed compute-intensive post-tape-out-flow runs (PTOF) jobs to apply various resolution enhancement technology (RET) techniques to incoming designs and convert these designs into photomask data that is ready for manufacturing. This process is performed on large compute clusters managed by a job scheduler. To minimize the compute cost of each PTOF job, various manual techniques are used to choose the best compute setup that produces the optimum hardware utilization and efficient runtime for that job. We introduce a machine learning (ML) solution that can provide CPU time prediction for these PTOF jobs, which can be used to provide compute cost estimations, provide recommendations for resources, and feed scheduling models. ML training is based on job-specific features extracted from production data, such as layout size, hierarchy, and operations, as well as meta-data like job type, technology node, and layer. The list of input features correlated to the prediction was evaluated, along with several ML techniques, across a wide variety of jobs. Integrating an ML-based CPU runtime prediction module into the production flow provides data that can be used to improve job priority decisions, raise runtime warnings due to hardware or other issues, and estimate compute cost for each job (which is especially useful in a cloud environment). Given the wide variation of expected runtimes for different types of jobs, replacing manual monitoring of jobs in tape-out operation with an integrated ML-based solution can improve both the productivity and efficiency of the PTOF process.
Advances in chip manufacturing processes continue to increase the number of vertices to deal with in Optical Proximity Correction (OPC) and Mask Data Preparation (MDP). In order to manage the processing time, OPC in sub-nanometer now requires employing tens of thousands of CPU cores. A slight mishap can force the job to be re-run. Increased complexity in the computing environment, along with the length of time a job spends in it, makes a job more susceptible to various sources of failures, while the re-run penalty is also growing with the design complexity. Checkpointing is a technique that saves the state of a system that continuously transitions to another state. The purpose of creating a checkpoint for a job is to make it possible to restart an interrupted job from the saved state at a later time. With checkpointing, if a running job encounters termination before its normal completion, be it due to a hardware failure or a human intervention to make resources available for an urgent job, it can resume from the checkpoint closest to the point of termination and continue to its completion. Checkpointing applications can include 1) resume flow where a terminated job can be resumed from the point close to the termination, 2) repair flow to fix OPC hotspot areas without having to process the entire chip and 3) cloud usage where job migration may be necessary. In this paper, we study the runtime and storage impact with checkpointing and demonstrate virtually no runtime impact and very minimal increase in filer storage. Furthermore, we show how checkpointing can significantly reduce runtime in OPC hotspot repair applications
As the semiconductor manufacturing industry moves towards advanced nodes with increasingly complex designs, users may experience an enormous increase in runtimes of mask data processing steps. This is true for Mask Process Correction (MPC)/Mask Data Preparation (MDP or fracture). Conventionally, in a high-volume production flow, the steps execute sequentially; a subsequent step waits for the preceding step to complete. In cases where the entire design does not need to be processed for the next step to begin, users may pipeline the steps to reduce total turn-around time. For example, if MPC and fracture are executed on a design, fracture commences only once MPC is complete on the entire design. An integrated, pipelined flow subsumes the runtimes associated with downstream fracture processing to the maximum possible capability of the computing resources. The integration is achieved by using a task-based pipeline that produces and consumes data without intermediate file exchange. It allows for in-memory processing which eliminates intermediate disk I/O operations, thereby making room for optimizations. This paper presents a comprehensive study of an integrated Curvilinear MPC (CLMPC) + IMS Multibeam Fracture (MBW) flow and demonstrates the runtime benefit with minimal impact on accuracy and file size over a conventional sequential flow [1,2]. We explore and demonstrate the runtime advantage from pipelining on a set of representative curvilinear/rectilinear designs by comparing sequential vs. pipelined execution of curvilinear MPC (CLMPC) and curvilinear fracture. A set of 11 designs are investigated to illustrate a substantial reduction in runtime while maintaining high-quality results.
Data volume and average data preparation time continue to trend upward with newer technology nodes. In the past decade, with file sizes measured in terabytes and network bandwidth requirements exceeding 40GB/s, mask synthesis operations have expanded their cluster capacity to thousands and even 10s of thousands of CPU cores. Efficient, scalable and flexible management of this expensive, high performance, distributed computing system is required in every stage of geometry processing - from layout polishing through Optical Proximity Correction (OPC), Mask Process Correction (MPC) and Mask Data Preparation (MDP) - to consistently meet tape out cycle time goals. The MDP step, being the final stage in the entire flow, has to write all of the pattern data into one or more disk files. This extremely I/O intensive section remains a significant portion of the processing time and creates a major challenge for the software from a scalability perspective. It is important to have a comprehensive solution that displays high scalability for large jobs and low overhead for small jobs, which is the ideal behavior in a typical production environment. In this paper we will discuss methods to address the former requirement, emphasizing the efficient use of high performance distributed file systems while minimizing the less scalable disk I/O operations. We will also discuss dynamic resource management and efficient job scheduling to address the latter requirement. Finally, we will demonstrate the use of a cluster management system to create a comprehensive data processing environment suitable to support large scale data processing requirements.
With CMOS technology nodes going further into the realm of sub-wavelength lithography, the need for compute power also increases to meet runtime requirements for reticle enhancement techniques and results validation. Expanding the mask data preparation (MDP) cluster size is an obvious solution to increase compute power, but this can lead to unforeseen events such as network bottlenecks, which must be taken into account. Advanced scalable solutions provided by optical proximity correction (OPC)/mask process correction (MPC) software are obviously critical, but other optimizations such as dynamic CPU allocations (DCA) based on real CPU needs, high-level jobs management, real-time resource monitoring, and bottleneck detection are also important factors for improving cluster utilization in order to meet runtime requirements and handle post-tapeout (PTO) workloads efficiently. In this paper, we will discuss tackling such efforts through various levels of the “cluster utilization stack” from low CPU levels to business levels to head towards maximizing cluster utilization and maintaining lean computing.
KEYWORDS: Optical proximity correction, Photomasks, Manufacturing, Data processing, Front end of line, Back end of line, Visualization, Design for manufacturability, Integrated circuits, Semiconductors
Delivering mask ready OPC corrected data to the mask shop on-time is critical for a foundry to meet the cycle time commitment for a new product. With current OPC compute resource sharing technology, different job scheduling algorithms are possible, such as, priority based resource allocation and fair share resource allocation. In order to maximize computer cluster efficiency, minimize the cost of the data processing and deliver data on schedule, the trade-offs of each scheduling algorithm need to be understood. Using actual production jobs, each of the scheduling algorithms will be tested in a production tape-out environment. Each scheduling algorithm will be judged on its ability to deliver data on schedule and the trade-offs associated with each method will be analyzed. It is now possible to introduce advance scheduling algorithms to the OPC data processing environment to meet the goals of on-time delivery of mask ready OPC data while maximizing efficiency and reducing cost.
KEYWORDS: Inspection, Data conversion, Data processing, Databases, Manufacturing, Explosives, Neodymium, Polonium, Photomask technology, Current controlled current source
Mask manufacturers are continuously challenged as a result of the explosive growth in mask pattern data volume.
This paper presents a new pipelined approach to mask data preparation for inspection that significantly reduces the
data preparation times compared to the conventional flows used today. The focus of this approach minimizes I/O
bottlenecks and allows for higher throughput on computer clusters. This solution is optimized for the industry
standard OASIS.MASK format.
These enhancements in the data processing flow, along with optimizations in the data preparation system
architecture, offer a more efficient and highly scalable solution for mask inspection data preparation.
The increasing demands for registration metrology for repeatability, accuracy, and resolution in order to be able to
perform measurements in the active area on production features have prompted the development of PROVETM, the nextgeneration
registration metrology tool that utilizes 193nm illumination and a metrology stage that is actively controlled
in all six degrees of freedom. PROVETM addresses full in-die capability for double patterning lithography and
sophisticated inverse-lithography schemes. Innovative approaches for image analysis, such as 2D correlation, have
been developed to achieve this demanding goal.
In order to take full advantage of the PROVETM resolution and measurement capabilities, a direct link to the mask data
preparation for job automation and marker identification is inevitable. This paper describes an integrated solution using
Synopsys' CATSR for extracting and preparing tool-specific job input data for PROVE. In addition to the standard
marking functionalities, CATSR supports the 2D correlation method by providing reference clips in OASIS.MASK
format.
Double Patterning Lithography (DPL) for next generation wafer exposure is placing greater demands on the
requirements for pattern placement accuracy on photomasks. Recent studies have shown that pattern placement accuracy
can be one of the largest components of systematic wafer overlay error. Since LELE or LFLE DPL technologies tighten
intra-field-wafer overlay requirements by as much as a factor of 2 (to 2 - 3nm for critical layers), minimizing all sources
of systematic overlay error has become critical. In addition to its impact on overlay performance, any significant pattern
displacement between the two exposures in a double patterning scheme will have a significant impact on CD uniformity,
another major area of concern for next-generation devices.
In the past, mask registration has been referenced to design data using relatively large, specially designed targets.
However, as shown in many previous papers [2], the true registration error of a next-generation reticle cannot be
sufficiently described by using today's sampling plans. In order to address this issue, it is mandatory to have In-Die
registration capability for next generation reticle registration. On this path to In-Die pattern placement metrology many
challenges have to be solved. One is the data preparation necessary to get the targets placed and marked within the
design, preparing for the later metrology step.
This paper demonstrates an automated way of performing In-Die registration metrology. This new approach allows more
flexible and higher density metrology so that pattern placement error is sufficiently well characterized.
As technology nodes go down to 45nm and below, mask metrology becomes more important as the critical features
decrease in size, while, at the same time, the number of measurements that need to be performed increases. OPC and
RET put further burden on metrology as it is typical to measure more than one dimension on a single feature. In order to
maximize the throughput of metrology tools and to keep up with the demand for more measurements, we have
implemented the ability to measure multiple CD sites within a field of view without any stage movement in fully
automated ways in a production environment. This in turn reduces total mask measurement time and helps to increase
tool capacity
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