With the integration of high speed Scanning Electron Microscope (SEM) based Automated Defect Redetection (ADR) in both high volume semiconductor manufacturing and Research and Development (R and D), the need for reliable SEM Automated Defect Classification (ADC) has grown tremendously in the past few years. In many high volume manufacturing facilities and R and D operations, defect inspection is performed on EBeam (EB), Bright Field (BF) or Dark Field (DF) defect inspection equipment. A comma separated value (CSV) file is created by both the patterned and non-patterned defect inspection tools. The defect inspection result file contains a list of the inspection anomalies detected during the inspection tools’ examination of each structure, or the examination of an entire wafers surface for non-patterned applications. This file is imported into the Defect Review Scanning Electron Microscope (DRSEM). Following the defect inspection result file import, the DRSEM automatically moves the wafer to each defect coordinate and performs ADR. During ADR the DRSEM operates in a reference mode, capturing a SEM image at the exact position of the anomalies coordinates and capturing a SEM image of a reference location in the center of the wafer. A Defect reference image is created based on the Reference image minus the Defect image. The exact coordinates of the defect is calculated based on the calculated defect position and the anomalies stage coordinate calculated when the high magnification SEM defect image is captured. The captured SEM image is processed through either DRSEM ADC binning, exporting to a Yield Analysis System (YAS), or a combination of both. Process Engineers, Yield Analysis Engineers or Failure Analysis Engineers will manually review the captured images to insure that either the YAS defect binning is accurately classifying the defects or that the DRSEM defect binning is accurately classifying the defects. This paper is an exploration of the feasibility of the utilization of a Hitachi RS4000 Defect Review SEM to perform Automatic Defect Classification with the objective of the total automated classification accuracy being greater than human based defect classification binning when the defects do not require multiple process step knowledge for accurate classification. The implementation of DRSEM ADC has the potential to improve the response time between defect detection and defect classification. Faster defect classification will allow for rapid response to yield anomalies that will ultimately reduce the wafer and/or the die yield.
This study explores the feasibility of Automated Defect Classification (ADC) with a Surface Scanning Inspection System (SSIS). The defect classification was based upon scattering sensitivity sizing curves created via modeling of the Bidirectional Reflectance Distribution Function (BRDF). The BRDF allowed for the creation of SSIS sensitivity/sizing curves based upon the optical properties of both the filmed wafer samples and the optical architecture of the SSIS.
The elimination of Polystyrene Latex Sphere (PSL) and Silica deposition on both filmed and bare Silicon wafers prior to SSIS recipe creation and ADC creates a challenge for light scattering surface intensity based defect binning. This study explored the theoretical maximal SSIS sensitivity based on native defect recipe creation in conjunction with the maximal sensitivity derived from BRDF modeling recipe creation.
Single film and film stack wafers were inspected with recipes based upon BRDF modeling. Following SSIS recipe creation, initially targeting maximal sensitivity, selected recipes were optimized to classify defects commonly found on non-patterned wafers. The results were utilized to determine the ADC binning accuracy of the native defects and evaluate the SSIS recipe creation methodology.
A statistically valid sample of defects from the final inspection results of each SSIS recipe and filmed substrate were reviewed post SSIS ADC processing on a Defect Review Scanning Electron Microscope (SEM). Native defect images were collected from each statistically valid defect bin category/size for SEM Review.
The data collected from the Defect Review SEM was utilized to determine the statistical purity and accuracy of each SSIS defect classification bin.
This paper explores both, commercial and technical, considerations of the elimination of PSL and Silica deposition as a precursor to SSIS recipe creation targeted towards ADC. Successful integration of SSIS ADC in conjunction with recipes created via BRDF modeling has the potential to dramatically reduce the workload requirements of a Defect Review SEM and save a significant amount of capital expenditure for 450mm SSIS recipe creation.
The continual increasing demands upon Plasma Etching systems to self-clean and continue Plasma Etching with minimal downtime allows for the examination of SiCN, SiO2 and SiN defectivity based upon Surface Scanning Inspection Systems (SSIS) wafer scan results. Historically all Surface Scanning Inspection System wafer scanning recipes have been based upon Polystyrene Spheres wafer deposition for each film stack and the subsequent creation of light scattering sizing response curves. This paper explores the feasibility of the elimination of Polystyrene Latex Sphere (PSL) and/or process particle deposition on both filmed and bare Silicon wafers prior to Surface Scanning Inspection System recipe creation. The study will explore the theoretical maximal Surface Scanning Inspection System sensitivity based on PSL recipe creation in conjunction with the maximal sensitivity derived from Bidirectional Reflectance Distribution Function (BRDF) maximal sensitivity modeling recipe creation. The surface roughness (Root Mean Square) of plasma etched wafers varies dependent upon the process film stack. Decrease of the root mean square value of the wafer sample surface equates to higher surface scanning inspection system sensitivity. Maximal sensitivity SSIS scan results from bare and filmed wafers inspected with recipes created based upon Polystyrene/Particle Deposition and recipes created based upon BRDF modeling will be overlaid against each other to determine maximal sensitivity and capture rate for each type of recipe that was created with differing recipe creation modes. A statistically valid sample of defects from each Surface Scanning Inspection system recipe creation mode and each bare wafer/filmed substrate will be reviewed post SSIS System processing on a Defect Review Scanning Electron Microscope (DRSEM). Native defects, Polystyrene Latex Spheres will be collected from each statistically valid defect bin category/size. The data collected from the DRSEM will be utilized to determine the maximum sensitivity capture rate for each recipe creation mode. Emphasis will be placed upon the sizing accuracy of PSL versus BRDF modeling results based upon automated DRSEM defect sizing. An examination the scattering response for both Mie and Rayleigh will be explored in relationship to the reported sizing variance of the SSIS to make a determination of the absolute sizing accuracy of the recipes there were generated based upon BRDF modeling. This paper explores both the commercial and technical considerations of the elimination of PSL deposition as a precursor to SSIS recipe creation. Successful integration of BRDF modeling into the technical aspect of SSIS recipe creation process has the potential to dramatically reduce the recipe creation timeline and vetting period. Integration of BRDF modeling has the potential to greatly reduce the overhead operation costs for High Volume Manufacturing sites by eliminating the associated costs of third party PSL deposition.
The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the standpoint of the generations of hundreds of SSIS recipes for the global member companies of ISMI, it is simply not economically viable to create all recipes based on PSL based light scattering response curves. This paper will explore the challenges/end results encountered with the PSL based SSIS recipe generation and compare those against the challenges/end results of SSIS recipes generated based strictly upon theoretical Bidirectional reflectance distribution function (BRDF) light scattering modeling. The BRDF modeling will allow for the creation of SSIS recipes without PSL deposition, which is greatly appealing for a multitude of both technical and commercial considerations. This paper will also explore the technical challenges of SSIS recipe generation based strictly upon BRDF modeling.
Physical vapor deposition (PVD) aluminum films present unique challenges when detecting particulate
defects with a Surface Scanning Inspection System (SSIS). Aluminum (Al) films 4500Å thick were
deposited on 300mm particle grade bare Si wafers at two temperatures using a Novellus Systems INOVA®
NExT,.. Film surface roughness and morphology measurements were performed using a Veeco Vx310®
atomic force microscope (AFM). AFM characterization found the high deposition temperature (TD) Al
roughness (Root Mean Square 16.5 nm) to be five-times rougher than the low-TD Al roughness (rms 3.7
nm). High-TD Al had grooves at the grain boundaries that were measured to be 20 to 80 nm deep.
Scanning electron microscopy (SEM) examination, with a Hitachi RS6000 defect review SEM, confirmed
the presence of pronounced grain grooves. SEM images established that the low-TD filmed wafers have
fine grains (0.1 to 0.3 um diameter) and the high-TD film wafers have fifty-times larger equiaxed plateletshape
grains (5 to 15 um diameter).
Calibrated Poly-Styrene Latex (PSL) spheres ranging in size from 90 nm to 1 μm were deposited in circular
patterns on the wafers using an aerosol deposition chamber. PSL sphere depositions at each spot were
controlled to yield 2000 to 5000 counts. A Hitachi LS9100® dark field full wafer SSIS was used to
experimentally determine the relationship of the PSL sphere scattered light intensity with S-polarized light,
a measure of scattering cross-section, with respect to the calibrated PSL sphere diameter. Comparison of
the SSIS scattered light versus PSL spot size calibration curves shows two distinct differences. Scattering
cross-section (intensity) of the PSL spheres increased on the low-TD Al film with smooth surface roughness
and the low-TD Al film defect detection sensitivity was 126 nm compared to 200 nm for the rougher high-
TD Al film. This can be explained by the higher signal to noise attributed to the smooth low-TD Al.
Dark field defect detection on surface scanning inspection systems is used to rapidly measure defectivity
data. The user generates a calibration curve on the SSIS to plot the intensity of the light scattering derived
at each National Institute of Standards and Technology (NIST) certified PSL deposition spot that was
deposited. It is not uncommon for the end user to embark upon the time consuming process of attempting
to "push" the maximal SSIS film specific sensitivity curve beyond the optical performance capability of the
SSIS.
Bidirectional reflectance distribution function (BRDF) light scattering modeling was utilized as a means of
determining the most appropriate polarity prior to the SSIS recipe creation process. The modeling utilized
the Al refractive index (n) and extinction coefficient (k) and the SSIS detector angles and laser wavelength.
The modeling results allowed predetermination of the maximal sensitivity for each different Al thickness
and eliminate unnecessary recipe modification trial-and-error in search of the SSIS maximal sensitivity.
The modeling accurately forecasted the optimal polarization and maximal sensitivity of the SSIS recipe,
which, by avoiding a trial and error approach, can result in a substantial savings in time and resources.
The methodology of Surface Scanning Inspection System (SSIS) for the Chemical Mechanical Polish
(CMP) Process is to inspect the wafers on a SSIS and then subsequently perform a Defect Review SEM
(DRS) review of the detected surface and subsurface anomalies. The subsequent defect review on a DRS
allows for the classification of defects into discrete classification bins. The challenge of utilizing an
automated DRSEM on micro and macro scratches resides in the accurate classification. When the DRSEM
Field of View (FOV) is too large or too small, the defect(s) may be incorrectly classified into the incorrect
defect classification bin.
An exploration of the feasibility of utilizing the Hitachi LS9100 Surface Scanning Inspection System to
automatically classify Chemical Mechanical Polishing induced scratches as a means of bypassing
subsequent Defect Review Scanning Electron Microscope Automatic Defect Classification steps is
evaluated as one of the key indices into the accelerated release of new slurry products from research and
development into full manufacturing
Given the current manufacturing technology roadmap and the competitiveness of the global semiconductor
manufacturing environment in conjunction with the semiconductor manufacturing market dynamics, the
market place continues to demand a reduced die manufacturing cost. This continuous pressure on lowering
die cost in turn drives an aggressive yield learning curve, a key component of which is defect reduction of
manufacturing induced anomalies. In order to meet and even exceed line and die yield targets there is a
need to revamp defect classification strategies and place a greater emphasize on increasing the accuracy
and purity of the Defect Review Scanning Electron Microscope (DRSEM) Automated Defect Classification
(ADC) results while placing less emphasis on the ADC results of patterned/un-patterned wafer inspection
systems. The increased emphasis on DRSEM ADC results allows for a high degree of automation and
consistency in the classification data and eliminates variance induced by the manufacturing staff.
This paper examines the use of SEM based Auto Defect Classification in a high volume manufacturing
environment as a key driver in the reduction of defect limited yields.
Measuring coating defects on two or more blanket film layers is difficult and can be misleading due to reflectivity
changes from the bottom layer, and surface roughness not present when the substrate is only polished silicon. To
improve signal-to-noise ratio and establish a lower limit for particle size detection, polystyrene latex (PSL) spheres are
deposited on the film stack. Particles as small as 54 nm were detectable on a stack 330-nm thick using a Hitachi LS
Series Surface Scanning Inspection System (SSIS) and RS5500 Defect Review Scanning Electron Microscope
(DRSEM). These systems have advanced capabilities enabling automated detection, classification, and characterization
of defects down to 30 nm or smaller on some substrates and films. Haze wafer maps are related to surface roughness and
reflectivity and show unusual asymmetries possibly caused by dispense problems or exhaust flow patterns during baking.
These maps can be helpful to find problems in the coating system, even if film thickness is on target. Preliminary testing
results are presented for a typical trilayer pattern stack for high-resolution 193-nm patterning consisting of a silicon spinon
hardmask (HM) layer on top of a spin-on carbon (SOC) layer. The majority of the defects were caused by bubble
formation within the HM that was modulated by process conditions used for these tests. A higher spin speed for the HM
coating produced lower defects, most likely due to a thinner film with less trapped solvent during baking, but this effect
will require more study, as it could also be due to a faster evaporation rate caused by higher airflow. Pre-wet, spin time,
and bake temperature did not produce significant effects within these tests, but showed trends requiring further study.
These advanced spin-on HM materials can be applied as thin as 15 to 20 nm due to their high etch selectivity. With the use of such high-resolution defect metrology, very subtle chemical interactions and process effects can be examined to find the ideal process conditions for both the SOC and HM layers.
One of the few remaining bastions of non-regulated Integrated Circuit defectivity is the wafer bevel. Recent internal
Integrated Circuit Manufacturing studies have suggested that the edge bevel may be responsible for as much as a two to
three percent yield loss during a defect excursion on the manufacturing line and a one to two percent yield loss during
ongoing wafer manufacturing.
A new generation of defect inspection equipment has been introduced to the Research and Development, Integrated
Circuit, MEM's and Si wafer manufacturing markets that has imparted the ability for the end equipment user to detect
defects located on the bevel of the wafer.
The inherent weakness of the current batch of wafer bevel inspection equipment is the lack of automatic discrete defect
classification data into multiple, significant classification bins and the lack of discrete elemental analysis data. Root
cause analysis is based on minimal discrete defect analysis as a surrogate for a statistically valid sampling of defects
from the bevel.
This paper provides a study of the methods employed with a Hitachi RS-5500EQEQ Defect Review Scanning Electron
Microscope (DRSEM) to automatically capture high resolution/high magnification images and collect elemental analysis
on a statistically valid sample of the discrete defects that were located by a bevel inspection system.
As the Integrated Circuit manufacturing market has begun a concerted effort toward the mass production of 45nm node
material, the emergence of inaccurate defect sizing and subsequent mis-identification of surface and subsurface defects
from Surface Scanning Inspection Systems (SSIS) has become a major impediment for accurate Scanning Electron
Microscope (SEM) Automated Defect Redetection (ADR) and Automated Defect Classification (ADC).
Due to the increased manufacturing cost of Silicon Wafers (Silicon on Insulator, Strained Silicon, Strained Silicon on
Oxide, Silicon on Silicon Germanium) and the desire from IC manufacturing companies for a continually increasing
level of Incoming Quality Assurance (IQA) wafer cleanliness, the cost of IC manufacturing has dramatically risen in
recent years.
The increased cost of manufacturing for both IC manufacturing and Silicon Wafer manufacturing is driving the
requirement for a high throughput Defect Review SEM that is able to independently overcome the defect sizing and
defect classification challenges from both the 45nm and 90nm nodes. The benefits of improved SEM ADR and ADC
performance must not come at the expense of the SSIS throughput.
This paper provides a study of the methods employed in multiple manufacturing lines to provide rapid feedback of yield
impacting defects, allowing for improved root cause analysis and improved fab productivity.
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