It is well known in the industry that the technology nodes from 30nm and below will require model based SRAF / OPC
for critical layers to meet production required process windows. Since the seminal paper by Saleh and Sayegh
thirty years ago, the idea of using inverse methods to solve mask layout problems has been receiving increasing attention
as design sizes have been steadily shrinking. ILT in its present form represents an attempt to construct the inverse
solution to a constrained problem where the constraints are all possible phenomena which can be simulated, including:
DOF, sidelobes, MRC, MEEF, EL, shot-count, and other effects. Given current manufacturing constraints and process
window requirements, inverse solutions must use all possible degrees of freedom to synthesize a mask.
Various forms of inverse solutions differ greatly with respect to lithographic performance and mask complexity. Factors
responsible for their differences include composition of the cost function that is minimized, constraints applied during
optimization to ensure MRC compliance and limit complexity, and the data structure used to represent mask patterns. In
this paper we describe the level set method to represent mask patterns, which allows the necessary degrees of freedom
for required lithographic performance, and show how to derive Manhattan mask patterns from it, which can be
manufactured with controllable complexity and limited shot-counts. We will demonstrate how full chip ILT masks can
control e-beam write-time to the level comparable to traditional OPC masks, providing a solution with maximized
lithographic performance and manageable cost of ownership that is vital to sub-30nm node IC manufacturing.
For low k1 lithography the resolution of critical patterns on large designs can require advanced resolution enhancement
techniques for masks including scattering bars, complicated mask edge segmentation and placement, etc. Often only a
portion of a large layout will need this sophisticated mask design (the hotspot), with the remainder of layout being
relatively simple for OPC methods to correct. In this paper we show how inverse lithography technology (ILT) can be
used to correct selected regions of a large design after standard OPC has been used to correct the simple portions of the
The hotspot approach allows a computationally intensive ILT to be used in a limited way to correct the most difficult
portions of a design. We will discuss the most important issues such as: model matching between ILT and OPC
corrections; transition region corrections near the ILT and OPC boundary region; mask complexity; total combined
runtime. We will show both simulated and actual wafer lithographic improvements in the hotspot regions.
For semiconductor IC manufacturing at sub-30nm and beyond, aggressive SRAFs are necessary to ensure sufficient
process window and yield. Models used for full chip Inverse Lithography Technology (ILT) or OPC with aggressive
SRAFs must predict both CDs and sidelobes accurately. Empirical models are traditionally designed to fit SEMmeasured
CDs, but may not extrapolate accurately enough for patterns not included in their calibration. This is
particularly important when using aggressive SRAFs, because adjusting an empirical parameter to improve fit to CDSEM
measurements of calibration patterns may worsen the model's ability to predict sidelobes reliably. Proper choice of
the physical phenomena to include in the model can improve its ability to predict sidelobes as well as CDs of critical
patterns on real design layouts. In the work presented here, we examine the effects of modeling certain chemical
processes in resist. We compare how a model used for ILT fits SEM CD measurements and predicts sidelobes for
patterns with aggressive SRAFs, with and without these physically-based modeling features. In addition to statistics
from fits to the calibration data, the comparison includes hot-spot checks performed with independent OPC verification
software, and SEM measurements of on-chip CD variation using masks created with ILT.
Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks
provide significantly better litho performance than traditional OPC masks. To enable ILT for production as one of the
leading candidates for low-k1 lithography, one major task to overcome is mask manufacturability including mask data
fracturing, MRC constraints, writing time, and inspection. In prior publications[4,5], it has been shown that the Inverse
Synthesizer (ISTM) product has the capability to adjust for mask complexity to make it more manufacturable while
maintaining the significant litho gains of nearly ideal ILT mask. The production readiness of ILT has been
demonstrated at full-chip level. To fully integrate ILT mask into production, a number of areas were investigated to
further reduce ILT mask complexity without compromising too much of process window. These areas include flexible
controls of SRAF placements with respect to local feature sizes, separate control of Manhattan mask segment length of
main and SRAF features, topology based variable segmentation length, and jog alignment. The impact of these
approaches on e-beam mask writing time and lithography performance is presented in the paper.
Due to shrinking design nodes and to some limitations of scanners, extreme off-axis illumination (OAI) required and
its use and implementation of assist features (AF) to solve depth of focus (DOF) problems for isolated features and
specific pitch regions is essential. But unfortunately, the strong periodic character of OAI illumination makes AF's print
more easily. Present OPC flows generate AFs before OPC, which is also causes some AF printing problems. At present,
mask manufacturers must downsize AF's below 30nm to solve this problem. This is challenging and increases mask cost.
We report on an AF-fixer tool which is able to check AF printability and correct weak points with minimal cost in
terms of DOF after OPC. We have devised an effective algorithm that removes printing AF's. It can not only search for
the best non-printing AF condition to meet the DOF spec, but also reports uncorrectable spots, which could be marked as
design errors. To limit correction times and to maximize DOF in full-chip correction, a process window (PW) model and
incremental OPC method are applied. This AF fixer, which suggests optimum AF in only weak point region, solves AF
printing problems economically and accurately.
In order to satisfy high density and cost effective production, extreme illumination condition, maximum sigma and OAI, is currently implemented at low k1 process. In this condition, minimal change of optical condition results in large difference of patterning. Specifically, blurring, intensity asymmetry and tele-centricity of illumination source cause deformation of some pitch patterns and CD asymmetry of semi-isolated patterns. In conventional modeling using ideal source optical model such as top-hat shape or profile, those data are regarded as noise terms since it is difficult to fit them well and such model inaccuracy produce OPC error. This paper provided results of the OPC performance using real source optical model obtained from a scanner. Real source image was filtered and normalized for easy handling. It was shown that we improved the model accuracy and significantly reduced the number of parameters. As a result, we increased process margin for sub-60nm device.
Design for Manufacturing (DFM) is being widely accepted as one of keywords in cutting edge lithography and OPC technologies. Although DFM seems to stem from designer's intensions to consider manufacturability and ultimately improve the yield, it must be well understood first by lithographers who have the responsibility of reliable printing for a given design on a wafer. Current lithographer's understanding of DFM can be thought of as a process worthy design, and the requirements set forth from this understanding needs to be well defined to a designer and fed forward as a necessary condition for a robust design. Provided that these rules are followed, a robust and process worthy design can be achieved as a result of such win-win feed-forward strategy. In this paper, we discuss a method on how to fully analyze a given design and determine whether it is process worthy, in other words DFM-worthy or not. Mask Error Enhancement Factor (MEEF), Through Focus MEEF (TF-MEEF) and Mean-To-Target (MTT) values for an initial tentative design provide good metrics to obtain a robust and process worthy design. Two remedies can be chosen as DFM solutions according to the aforementioned analysis results: modify the original design or manipulate the layout within a design tolerance during OPC. We will discuss on how to visualize the analyzed results for the robust and process worthy OPC with some relevant examples. In our discussions, however, we assumed that the robust model be being used for each design verification, and such a model derived with more physical parameters that correlates better to real exposure behavior. The DFM can be viewed as flattening the TF-MEEF across the design.
As k1 factor approaches the theoretical limit, optical proximity correction (OPC) treatments necessary to maintain dimensional tolerances involve increasingly complex correction shapes. This translates to more detailed, or larger mask pattern databases. Moreover, development of exposure tools lags behind the shrinkage of device. This may result in dwindling of process margin in lighographic process despite using all possible resolution enhancement techniques (RETs). Although model-based OPC may lose its effectiveness in case of narrower photolithographic process margin, model-based OPC is recognized as a robust tool to cope with the diversity of layout. By the way, in case of narrower photolithographic process margin, model-based OPC lose its effectiveness. To enhance the usefulness of the OPC, we need to overcome many obstacles. It is supposed that the original layout be designed friendly to lithography to enhance the process margin using aggressive RETs, and is amended by model-based OPC to suppress the proximity effect. But, some constraints are found during an OPC procedure. Ultimately, unless the original lithgraphy friendly layout (LFL) is corrected in terms of pitches and shapes, the lithography process is out of process window as well as makes pattern fidelity poor. This paper emphasizes that the application of model-based OPC requires a particular and unique layout configuration to preserve the process margin in the low k1 process.
The on-chip variation (OCV) should be critically controlled to obtain the high speed performance in logic devices. The variation from proximity dominantly contributes to OCV. This proximity effect can be compensated by applying well-treated optical proximity correction (OPC). Therefore, the accuracy of OPC is needed, and methods to enhance its result have to be devised. The optical proximity behaviors are severely varied according to the material and optical conditions. In point of material, the proximity property is affected by species of photo-resist (PR) and change of post exposure bake (PEB) conditions. 3σ values of proximity variation are changed from 9.3 nm to 15.2 nm according to PR species. Also, proximity variations change from 16.2 nm to 13.8 nm is observed according to PEB condition. Proximity variations changes of 11.6 nm and 15.2 nm are measured by changing the illumination condition. In order not to seriously deteriorate OPC, these factors should be fixed after the OPC rules are extracted. Proximity variations of 11.4 nm, 13.9 nm and 15.2 nm are observed for the mask mean-to-targets (MTT) of 0 nm, 2nm, and 4nm, respectively. The decrease the OPC grid size enhances the correction resolution and the OCV is reduced. The selective bias rule is generated by model using grid size of 1 nm and 0.5 nm. For the nominal CD of 87 nm, proximity variations are measured to be 14.6 nm and 11.4 nm for 1 nm and 0.5 nm grid sizes, respectively. The enhancement amount of proximity variations are 9.2 nm corresponding to 39% improvement. The CD uniformity improvement for adopting the small grid size is confirmed by measuring the CD uniformity on real SRAM pattern. CD uniformities are measured 11nm and 9.1nm for grid size of 1 nm and 0.5 nm, respectively. 22% improvement of the CD uniformity is achieved.
KrF lithography around 0.3k1 was studied using high transmittance attenuated phase shifting mask(att.PSM). Although gradual transition to the more high NA KrF scanner or ArF scanner takes place, the strong requests for the timely process development to keep up with the rapid shrinkage of device drive the extension of lithography technology to the lower k1; 0.3 or even below.
Under the given illumination condition, aerial image contrasts for varying design rules(D/R) can be related to the transmittance of att.PSM. In other words, there exists an optimum mask transmittance for each D/R, from which we try to seek the feasible way of extension to the lower k1.
We will cover the EL(Exposure Latitude), the MEEF(Mask Error Enhancement Factor), and also discuss an interesting behavior of the N-M offset in utilizing high transmittance att.PSM in the low k1 node. We used the att.PSM of 20% transmittance, as a special case experiment, to investigate the effect of high transmittance around 0.3k1 lithography. This study may facilitate the application of high transmittance att.PSM to the lower k1 and contribute to extending the lifetime of optical lithography.
It is well known that flare, which increases the background intensity and loses the image contrast, degrades the pattern fidelity and CD uniformity. Usually there is little mid and long-range flare at the initial exposure tool introduction except the short-range flare, so called, aberration. However, flare effect is observed in used exposure tools. To estimate the influence of flare, both lens quality of the exposure tool and mask pattern layout with various open ratios are important parameters to be considered. So it is very crucial to make a standard mask layout to measure the flare value as a tool specification. So far, CD variation of the long-range flare has been measured and reported. The long-range flare includes the average influence of the short and mid-range flare and affects more than several hundred- micron distances. Recently it is observed that lens contamination is a dominant component among sources of flare and induced by the pattern layout with its different open ratio. Being contaminated, the lens malfunctions with various types of scattering sources. These scattering sources make the mid and long range flare. This type of flare source has time dependence. If there are proper monitoring methods for the flare measurement, it is possible to maintain the lens quality within the limit of mid range flare. In addition, matching the flare value to CD distribution is not easy because there is no standard measurement method to distinguish the short and mid-range flare from the long-range one. In this paper a LOcal Area Flare Evaluation Reticle (LOAFER) method is suggested. The LOAFER is designed to measure the local area flare of the lens, that is, the short and mid-range flare and the local flare distribution of the exposure tool lens can be characterized. Then matching the result to the real device pattern will be introduced.