Overlay measurement error is a critical technical issue in the production of highly stacked semiconductor devices, including VNAND memory chips, CMOS image sensors, and three-dimensional packages. Complicated device structure and stacked structure increase the measurement error of overlay alignment mark position. Inverse optical design or system optimization is required to improve overlay metrology accuracy and measurement robustness. Illumination light source wavelength, source bandwidth, illumination mode, and imaging pupil filter can be optimized for overlay metrology signal with various kinds of complicated device structure. We proposed a practical inverse optical solution to improve the accuracy of overlay metrology. The inverse optical design consists of overlay mark reflectance estimation and optical configuration optimization. Both the estimation and optimization are accelerated using a quasi-two-dimensional partially coherent imaging model. We achieve more than 50 times faster imaging simulation acceleration compared to a conventional simulation algorithm for partially coherent illumination imaging with practical accuracy. Further improvement can be realized with an introduce of an overlay mark reflectance matrix computed by a rigorous electromagnetic analysis simulation for each specific device structure. This robust and practical inverse solution can help improve the overlay accuracy and manufacturing yield of highly complex three-dimensional devices.
The laser stealth dicing system is a unique wafer processing system to enable high-throughput and debris-free wafer dicing. In the laser stealth dicing system, a focused pulsed laser forms a modification layer and cracks inside a silicon wafer. During pulsed laser radiation and wafer scanning, cracks formed in the previous shot interfere with a focusing laser pulse on a defocus plane. As a result, a part of interacted laser beam scatters, generating back-side splash defects on the device layer. An asymmetric beam shaping of defocused spot becomes necessary to minimize the splash defects. At the same time, the focused spot should maintain sufficiently small focused spot size to generate a modified layer inside the silicon wafer. This paper presents a concept of an innovative focusing spot shaping with an asymmetrical pupil phase filter which is individually optimized for both defocused and focused spots. We optimized the phase filter to generate a threedimensionally- asymmetrical focused spot which deforms defocused spot with a near diffraction-limited focal spot size. The through-focus spot shaping technique is enable to minimize splash defects and improve the yield of the laser wafer dicing process.
Advances in the semiconductor industry have led the wafer inspection technology to the limit of nanometer-scale defect detection, which is far beyond the diffraction limit. In this regime, the signal-to-noise ratio (SNR) is the figure-of-merit to determine whether the optical system can detect a single nanometer-scale defect. In this paper, we investigated the SNR properties of various line defects using the dark-field inspection with tailored polarized illumination by simulation and experiment. Conventional crossed Nicols configuration with linear polarized illumination and crossed analyzer can minimize background scattering noise and maximize line defect signal only for a specific kind of line defect such as gap or bridge due to strong polarization dependence on a line and space (L/S) pattern. The nulling elliptically polarized illumination is optimized to suppress background scattering noise moderately and maintain defect signal intensity at the same time. We confirmed SNR improvement for both 10 nm open and bridge defects on 40 nm line and space silicon pattern with 40 nm depth. There was a good agreement between our simulation results and experimental results. We experimentally confirmed SNR ~ 4 for both line gap and bridge defect detection on 40 nm L/S patterned wafer with the fixed nulling illumination.
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