Dr. Sungho Lee Profile

Dr. Sungho Lee

at Samsung Advanced Institute of Technology

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Author

Publications (14)

Proceedings Article | 11 May 2009 Paper

Double patterning addressing imaging challenges for near- and sub-k1=0.25 node layouts

Beom-Seok Seo, Dae-Kwon Kang, Myung-Soo Noh, Sung-Ho Lee, Christopher Cork, Gerald LukPat, Alexander Miloslavsky, Xiaohai Li, Kevin Lucas, Sooryong Lee

Proc. SPIE. 7379, Photomask and Next-Generation Lithography Mask Technology XVI

KEYWORDS: Lithography, Logic, Optical lithography, Etching, Metals, Silicon, Manufacturing, Photomasks, Double patterning technology, Optical proximity correction

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A variety of innovations including the reduction of actinic wavelength, an increase in lens NA, an introduction of immersion process, and an aggressive OPC/RET technique have enabled device shrinkage down to the current 45nm node. The immaturity of EUV and high index immersion, have made logic manufacturers look at other ways of leveraging existing exposure technologies as they strive to develop process technology for 32nm and below. For design rules for sub-nodes from 32nm to 22nm, the need to define critical layers with double photolithography and etch process becomes increasingly evident. Double patterning can come in a variety of forms or 'flavors'. For 32/28nm node, the patterning of 2D features is so challenging that opposing line-ends can only be defined using an additional litho and etch step to cut them. For 22nm node, even line/space gratings are below the theoretical k1=0.25 imaging limit. Therefore pitch-doubling double patterning decomposition is absolutely required. Each double patterning technology has its own set of challenges. Most of all, an existing design often cannot be shrunk blindly and then successfully decomposed, so an additional set of restrictions is required to make layouts double patterning compliant. To decompose a logic layout into two masks, polygons often need to be cut so that they can be patterned using both masks. The electric performance of this cut circuitry may be highly dependent on the quality of layout decomposition, the circuit characteristics and its sensitivity to misalignment between the two patterning steps. We used representative logic layouts of metal level and realistic models to demonstrate the issues involved and attempt to define formal rules to help enable lineend splitting and pitch-doubling double patterning decomposition. This study used a variety of shrink approaches to existing legacy layouts to evaluate double patterning compliance and a careful set-up of parameters for the pitch splitting decomposition engine. The quality of the resultant imaging was tuned using double patterning aware OPC and printability verification tools.

Proceedings Article | 17 October 2008 Paper

Pixel-based SRAF implementation for 32nm lithography process

Byung-Sung Kim, Yoo-Hyun Kim, Sung-Ho Lee, Sung-Il Kim, Sang-Rok Ha, Juhwan Kim, Alexander Tritchkov

Proc. SPIE. 7122, Photomask Technology 2008

KEYWORDS: Lithography, Photovoltaics, Logic, Manufacturing, Photomasks, Image enhancement, Double patterning technology, Optical proximity correction, SRAF, Semiconducting wafers

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Proceedings Article | 19 May 2008 Paper

A new approach to the DFM for the metals

No-Young Chung, Hee-Sang Bae, Beum-Seok Seo, Sung-Ho Lee, Sung-Il Kim, Sun-Yong Lee

Proc. SPIE. 7028, Photomask and Next-Generation Lithography Mask Technology XV

KEYWORDS: Optical lithography, Calibration, Etching, Metals, 3D modeling, Bridges, Design for manufacturing, Optical proximity correction, Optimization (mathematics), Process modeling

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Metal layers have some drawbacks in building up model based OPC (MBOPC) because metal layers are mainly composed of 2 dimensional (2D) patterns which show modeling inaccuracy and the difficulty of fragment optimization compared with 1-dimensional patterns. As a result, metal layers have considerable hot spots such as pinch, bridge and insufficient contact overlap. The modeling inaccuracy of 2D patterns results from a few reasons like measurement noise, inaccurate optical simulation and empirical resist modeling etc. The fragment optimization operated by rule does not control automatically corner rounding problems induced by small jogs of 2D patterns. The design for manufacturability (DFM) is known to provide a solution to overcome these problems. One of engines operating the DFM is MBOPC, which is made by an empirical process model and offers the process variation counter map simulated by the MBOPC engine. However, the accuracy of the simulation is quite low because we cannot avoid over-corrected patterns generated inevitably with the empirical model. In order to detect and correct the hot spots caused by the design itself, that is, the inherent function of the DFM, it is necessary to provide the OPC engine of the physical model with the optimized illumination condition to rule out empirical effect. Physical model is more emphasized in case of process window simulation because of its accuracy in the edge boundary of process window. One of important function of DFM for the metal layers is to enhance the contact overlap margin which can be influenced by the lithography process such as line end shortening, corner rounding effect and miss-alignment. Etch process is also a significant parameter of contact overlap. Calibrated process model is very effective to detect the insufficient contact overlap with process window. In this paper, MBOPC of sub-45nm node metal layers is studied to provide the effective DFM engine. The DFM flow with renewed MBOPC engine will show the improved process window and large contact overlap margin and will also make it possible to search and correct just patterns capable of decreasing the process window by only layout defect itself.

Proceedings Article | 30 October 2007 Paper

The improvement of OPC accuracy and stability by the model parameters' analysis and optimization

No-Young Chung, Woon-Hyuk Choi, Sung-Ho Lee, Sung-Il Kim, Sun-Yong Lee

Proc. SPIE. 6730, Photomask Technology 2007

KEYWORDS: Wafer-level optics, Data modeling, Polarization, Databases, Optical proximity correction, Optimization (mathematics), Semiconducting wafers, Statistical modeling, System on a chip, Instrument modeling

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The OPC model is very critical in the sub 45nm device because the Critical Dimension Uniformity (CDU) is so tight to meet the device performance and the process window latitude for the production level. The OPC model is generally composed of an optical model and a resist model. Each of them has physical terms to be calculated without any wafer data and empirical terms to be fitted with real wafer data to make the optical modeling and the resist modeling. Empirical terms are usually related to the OPC accuracy, but are likely to be overestimated with the wafer data and so those terms can deteriorate OPC stability in case of being overestimated by a small cost function. Several physical terms have been used with ideal value in the optical property and even weren't be considered because those parameters didn't give a critical impact on the OPC accuracy, but these parameters become necessary to be applied to the OPC modeling at the low k1 process. Currently, real optic parameter instead of ideal optical parameter like the laser bandwidth, source map, pupil polarization including the phase and intensity difference start to be measured and those real measured value are used for the OPC modeling. These measured values can improve the model accuracy and stability. In the other hand these parameters can make the OPC model to overcorrect the process proximity errors without careful handling. The laser bandwidth, source map, pupil polarization, and focus centering for the optical modeling are analyzed and the sample data weight scheme and resist model terms are investigated, too. The image blurring by actual laser bandwidth in the exposure system is modeled and the modeling result shows that the extraction of the 2D patterns is necessary to get a reasonable result due to the 2D patterns' measurement noise in the SEM. The source map data from the exposure machine shows lots of horizontal and vertical intensity difference and this phenomenon must come from the measurement noise because this huge intensity difference can't be caused by the scanner system with respect to the X-Y intensity difference specification in the scanner. Therefore this source map should be well organized for the OPC modeling and a manipulated source map improves the horizontal and vertical mask bias and even OPC convergence. The focus parameter which is critical for the process window OPC and ORC should be matched to the tilted Bossung plot which is caused by uncorrectable aberration to predict the CD change in the through focus with a new devised method. Pupil polarization data can be applied into the OPC modeling and this parameter is also used for the unpolarized source and the polarized source and specially this parameter helps Apodization loss to be 0 and is evaluated for the effect into the modeling. With the analysis and optimization about the model parameters the robust model is achieved in the sub 45nm device node.

Proceedings Article | 27 March 2007 Paper

The gate CD uniformity improvement by the layout retarget with refer to the litho process

No-Young Chung, Yeon-Ju Yoon, Sung-Ho Lee, Sung-Il Kim, Sang-Rok Ha, Sun-Yong Lee

Proc. SPIE. 6520, Optical Microlithography XX

KEYWORDS: Optical lithography, Calibration, Error analysis, Computer simulations, Optical proximity correction, Critical dimension metrology, Optimization (mathematics), Semiconducting wafers, Tolerancing, Process modeling

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As the minimum pitch size becomes smaller, the gate-poly critical dimension uniformity (CDU) is a critical parameter for the device performance and an important indicator of the OPC capability. From the photolithographic point of view, the root causes of increasing gate-poly CDU is due to corner rounding effects, ripples, misalignment between the gate-poly and active layers. The corner rounding effect of the gate-poly region on the active can be severe for the sub L50 device because the space between the active layer and the gate-poly layer becomes narrow. To correct these effects caused by litho-process the advanced OPC technique and the design rule limitation should be optimized. The OPC method which can be used to improve gate-poly CDU is defined as "Litho Process-aware OPC for the Gate-Poly CDU improvement" in this paper. The pixel based simulation algorithm which gives lots of information compared to the sparse simulation algorithm is used for the OPC and ORC. The design rule for the space limitation from RX to PC is evaluated with its own litho-process model and this evaluation result has to be reflected to the design rule and the OPC recipe to manipulate the polygons is also necessary. Additionally if misalignment exists in the minimum space between the active layer and gate-poly layer during the photo process, this corner rounding effect can be more serious, so this misalignment accounted to reduce the corner rounding effect on the gate-poly CDU. The redundant field poly polygon enclosing the contact can be cut by keeping the design rule for the overlap margin between the poly layer and the contact layer. The miss-alignment effect can be considered indirectly by sizing the active layer. The OPC convergence technique is also used to reduce the ripple phenomenon close to the concave corner and line end. As a result of retargeting to accommodate a corner rounding effects, ripple effects and misalignment correction led to an improved gate-poly CDU for a sub-50nm device.

Proceedings Article | 27 March 2007 Paper

Size tolerance of sub-resolution assist features for sub-50-nm node device

Byung-Sung Kim, Sung-Ho Lee, Hong-Jae Shin, Nae-In Lee

Proc. SPIE. 6520, Optical Microlithography XX

KEYWORDS: Lithography, Lithographic illumination, Control systems, Photomasks, SRAF, Critical dimension metrology, Semiconducting wafers, Tolerancing, Electromagnetism, Phase shifts

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Proceedings Article | 21 March 2007 Paper

Lithography enhanced manufacturability analysis by using multilevel simulated contours

Beom-Seok Seo, Woon-Hyuk Choi, Jong-Woon Park, Soung-Su Woo, Sung-Ho Lee

Proc. SPIE. 6521, Design for Manufacturability through Design-Process Integration

KEYWORDS: Lithography, Logic, Diffusion, Manufacturing, Electroluminescence, Photomasks, Optical proximity correction, Critical dimension metrology, Resolution enhancement technologies, Design for manufacturability

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Proceedings Article | 12 June 2003 Paper

Improvement of pattern collapse in sub-100-nm nodes

Myoung-Ho Jung, Sung-Ho Lee, Hyun-Woo Kim, Sang-Gyun Woo, Han-Ku Cho, Woo-Sung Han

Proc. SPIE. 5039, Advances in Resist Technology and Processing XX

KEYWORDS: Semiconductors, Lithography, Etching, Capillaries, Scanners, Coating, Critical dimension metrology, Photoresist processing, Semiconducting wafers, Liquids

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Proceedings Article | 12 June 2003 Paper

Comparison of ArF bilayer resists for sub-90-nm L/S fabrication

Jin Hong, Hyun-Woo Kim, Sung-Ho Lee, Sang-Gyun Woo, Han-Ku Cho, Woo-Sung Han

Proc. SPIE. 5039, Advances in Resist Technology and Processing XX

KEYWORDS: Lithography, Optical lithography, Etching, Silicon, Chemistry, Resistance, Oxygen, Scanning electron microscopy, Photoresist processing, Plasma

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Proceedings Article | 24 July 2002 Paper

Implementation of the ArF resists based on VEMA for sub-100-nm device

Hyun-Woo Kim, Sook Lee, Sang-Jun Choi, Sung-Ho Lee, Yool Kang, Sang-Gyun Woo, Dongseok Nam, Yun-Sook Chae, Jisoo Kim, Joo-Tae Moon, Robert Kavanagh, George Barclay

Proc. SPIE. 4690, Advances in Resist Technology and Processing XIX

KEYWORDS: Lithography, Etching, Dry etching, Polymers, Scanners, Chemistry, Manufacturing, Resistance, Scanning electron microscopy, Line edge roughness

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Proceedings Article | 24 July 2002 Paper

Novel surface silylation process for chemically amplified photoresist

Sung-Ho Lee, Jin Hong, Sang-Gyun Woo, Hang-Goo Cho, Woo-Sung Han

Proc. SPIE. 4690, Advances in Resist Technology and Processing XIX

KEYWORDS: Etching, Annealing, Silicon, Resistance, Oxygen, Silicon films, Critical dimension metrology, Line edge roughness, Photoresist processing, Plasma

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Proceedings Article | 24 August 2001 Paper

Improved lithographic performance for resists based on polymers having a vinyl ether-maleic anhydride (VEMA) backbone

Hyun-Woo Kim, Sang-Jun Choi, Dong-Won Jung, Sook Lee, Sung-Ho Lee, Yool Kang, Sang-Gyun Woo, Joo-Tae Moon, Robert Kavanagh, George Barclay, George Orsula, Joe Mattia, Stefan Caporale, Timothy Adams, Tsutomu Tanaka, Doris Kang

Proc. SPIE. 4345, Advances in Resist Technology and Processing XVIII

KEYWORDS: Oxides, Lithography, Etching, Dry etching, Polymers, Chemistry, Manufacturing, Resistance, Line edge roughness, Resist chemistry

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Proceedings Article | 24 August 2001 Paper

Novel 193-nm photoresist based on Olefin-containing lactones

Kwang-Sub Yoon, Dong-Won Jung, Sook Lee, Sung-Ho Lee, Sang-Jun Choi, Sang-Gyun Woo, Joo-Tae Moon

Proc. SPIE. 4345, Advances in Resist Technology and Processing XVIII

KEYWORDS: Oxides, Lithography, Etching, Dry etching, Polymers, Resistance, Photoresist materials, Polymerization, Chlorine, Fluorine

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Proceedings Article | 22 January 2001 Paper

Effect of mask reduction ratio in alternating phase-shift masks

In-Gyun Shin, Sung-Ho Lee, Yong-Hoon Kim, Seong-Woon Choi, Woo-Sung Han, Jung-Min Sohn, Tong-Kun Lim

Proc. SPIE. 4186, 20th Annual BACUS Symposium on Photomask Technology

KEYWORDS: Optical lithography, Scattering, Quartz, Manufacturing, Chromium, Image analysis, Solids, Photomasks, Tolerancing, Phase shifts

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Showing 5 of 14 publications

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