As the design node of memory device shrinks, OPC model accuracy is becoming ever more critical from development to manufacturing. To improve the model accuracy, more and more physical effects are analyzed and terms for those physical effects are added. But it is unachievable to capture the complete physical effects. In this study, deep neural network is employed and studied to improve model accuracy. Regularization is achieved using physical guidance model. To address overfitting issue, high volume of contour based edge placement (EP) gauges (>10K) are generated using fast eBeam tool (eP5) and metrology processing software (MXP) without increasing turnaround time. It is shown that the new approach improved model accuracy by >47% compared to traditional approach on >1.4K verification gauges.
The insertion of SRAF(Sub-Resolution Assist Feature) is one of the most frequently used method to enlarge the process window area. In most cases, the size of SRAF is proportional to the focus margin of drawn patterns. However, there is a trade-off between the SRAF size and SRAF printing, because SRAF is not supposed to be patterned on a wafer. For this reason, a lot of OPC engineers have been tried to put bigger and more SRAFs within the limits of the possible. The fact that many papers about predicting SRAF printability have been published recent years reflects this circumstance. Pattern dummy is inserted to enhance the lithographic process margin and CD uniformity unlike CMP dummy for uniform metal line height. It is ordinary to put pattern dummy at the designated location under consideration of the pitch of real patterns at design step. However, it is not always desirable to generate pattern dummies based on rules at the lithographic point of view. In this paper, we introduce the model based pattern dummy insertion method, which is putting pattern dummies at the location that model based SRAF is located. We applied the model based pattern dummy to the layers in logic devices, and studied which layer is more efficient for the insertion of dummies.
The contact hole patterning has been huge challenge in the photolithography since sub-100nm node device. There are many difficulties for NA (Numerical Aperture) and illumination optimization, especially since dense and sparse contact holes are mixed in the same mask. The high NA and OAI (Off Axis Illumination) have strong improvements for pattern fidelity and process margin in case of dense contact holes but DoF (Depth of Focus) margin is a problem for sparse patterns. The lithography engineers have two ways to overcome these contact holes patterning problems. The one is using the resist techniques such as resist thermal flow, SAFIER (Shrink Assist Techniques for Enhanced Resolution), RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) and the other is optimizing illumination and mask layout such as SRAF (Sub Resolution Assist Feature), OAI and PSM (Phase Shift Mask), double exposure. This paper will discuss contact hole patterning results using a combination OAI and SRAF with KrF.