Proceedings Article | 15 May 2007
Proc. SPIE. 6607, Photomask and Next-Generation Lithography Mask Technology XIV
KEYWORDS: Lithography, Diffraction, Design for manufacturing, Photomasks, Image enhancement, Optical proximity correction, Nanoimprint lithography, Critical dimension metrology, Semiconducting wafers, Fiber optic illuminators
Several criteria are applied to optimize the best illumination and bias condition for a layer. Normalized image log-slope
(NILS) and mask error enhancement factor (MEEF) are promising candidates to simply decide the optimized condition.
NILS represents imaging capability and MEEF represents the mask uniformity influence on wafer image. MEEF has
inversely relationship with NILS, but the optimized point of NILS does not exactly coincide with that of MEEF. Besides
NILS and MEEF, the depth of focus (DoF) is an important factor for defining the process margin. The process window
(PW) is expressed by DoF and exposure Latitude (EL). PW is general parameter used to determine the best lithographic
condition. Large EL can be obtained at the condition with good image performance. In order to include mask uniformity
effect in PW analysis, the common PW overlapping the final layout with positive and negative biased layouts is adopted.
Starting with the minimum NA, sigma and threshold, OPC is performed to satisfy the target layout using aerial image
model, and the final OPCed layout is obtained. The positive and negative biased layouts are generated from the final
OPCed layout. The bias limit is determined considering mask uniformity. The common PW obtained by overlapping the
final layout with positive and negative biased layouts is calculated. Then, NA, sigma and threshold are increased until
the maximum values are reached. The common PW at each NA, sigma and threshold value is obtained using the same
flow sequence. Comparing among calculated PWs, the NA, sigma and threshold of the maximum PW can be chosen as
the best illuminator and bias condition. In this paper, the optimized illumination and bias condition is determined using
PW for 60 nm memory device. The process flow is implemented by an OPC tool. By using the OPC tool for the
illuminator optimization, the actual layout and multiple monitoring points can be measured. In spite of a large number of
calculations, the fast calculation speed can be obtained by using the distributed process.
