Model-driven target optimization using an ILT hotspot fixer is applied to line collapsing defects of 2-
dimensional randomtest pattern of a very low K1 process. The target is moved by minimizing the process
variation band and the pitches of hotspot points are relaxed.The image quality improvement is thenchecked.
Model driven target optimized NILS and MEEF at the weakest hotspot point are improved to 1.22 and 5.5
from the values 0.79 and 10.6 of a traditional OPCwith advanced solver, respectively. The pattern collapsing
hotspot is then validated to be repaired by optimizing target position. A full hotspot fixer flow including
model-driven target optimization using ILT can also be extended into DFM applications.
Traditional rule-based and model-based OPC methods only simulate in a very local area (generally less than 1um) to identify and correct for systematic optical or process problems. Despite this limitation, however, these methods have been very successful for many technology generations and have been a major reason for the industry being able to tremendously push down lithographic K1. This is also enabled by overall good across-exposure field lithographic process control which has been able to minimize longer range effects across the field. Now, however, the situation has now become more complex. The lithographic single exposure resolution limit with 1.35NA tools remains about 80nm pitch but the final wafer dimensions and final wafer pitches required in advanced technologies continue to scale down. This is putting severe strain on lithographic process and OPC CD control. Therefore, formerly less important 2nd order effects are now starting to have significant CD control impact if not corrected for. In this paper, we provide examples and discussion of how optical and chemical flare related effects are becoming more problematic, especially at the boundaries of large, dense memory arrays. We then introduce a practical correction method for these systematic effects which reuses some of the recent long range effect correcting OPC techniques developed for EUV pattern correction (such as EUV flare). We next provide analysis of the benefits of these OPC methods for chemical flare issues in 193nm lithography very low K1 lithography. Finally, we summarize our work and briefly mention possible future extensions.
It is well known in the industry that the technology nodes from 30nm and below will require model based SRAF / OPC
for critical layers to meet production required process windows. Since the seminal paper by Saleh and Sayegh
thirty years ago, the idea of using inverse methods to solve mask layout problems has been receiving increasing attention
as design sizes have been steadily shrinking. ILT in its present form represents an attempt to construct the inverse
solution to a constrained problem where the constraints are all possible phenomena which can be simulated, including:
DOF, sidelobes, MRC, MEEF, EL, shot-count, and other effects. Given current manufacturing constraints and process
window requirements, inverse solutions must use all possible degrees of freedom to synthesize a mask.
Various forms of inverse solutions differ greatly with respect to lithographic performance and mask complexity. Factors
responsible for their differences include composition of the cost function that is minimized, constraints applied during
optimization to ensure MRC compliance and limit complexity, and the data structure used to represent mask patterns. In
this paper we describe the level set method to represent mask patterns, which allows the necessary degrees of freedom
for required lithographic performance, and show how to derive Manhattan mask patterns from it, which can be
manufactured with controllable complexity and limited shot-counts. We will demonstrate how full chip ILT masks can
control e-beam write-time to the level comparable to traditional OPC masks, providing a solution with maximized
lithographic performance and manageable cost of ownership that is vital to sub-30nm node IC manufacturing.
For semiconductor IC manufacturing at sub-30nm and beyond, aggressive SRAFs are necessary to ensure sufficient
process window and yield. Models used for full chip Inverse Lithography Technology (ILT) or OPC with aggressive
SRAFs must predict both CDs and sidelobes accurately. Empirical models are traditionally designed to fit SEMmeasured
CDs, but may not extrapolate accurately enough for patterns not included in their calibration. This is
particularly important when using aggressive SRAFs, because adjusting an empirical parameter to improve fit to CDSEM
measurements of calibration patterns may worsen the model's ability to predict sidelobes reliably. Proper choice of
the physical phenomena to include in the model can improve its ability to predict sidelobes as well as CDs of critical
patterns on real design layouts. In the work presented here, we examine the effects of modeling certain chemical
processes in resist. We compare how a model used for ILT fits SEM CD measurements and predicts sidelobes for
patterns with aggressive SRAFs, with and without these physically-based modeling features. In addition to statistics
from fits to the calibration data, the comparison includes hot-spot checks performed with independent OPC verification
software, and SEM measurements of on-chip CD variation using masks created with ILT.
OPC models with and without thick mask effect (3D-mask effect) are compared in their prediction capabilities of actual
2D patterns. We give some examples in which thin-mask models fail to compensate the 3D-mask effect. The models
without 3D-mask effect show good model residual error, but fail to predict some critical CD tendencies. Rigorous
simulation predicts the observed CD tendencies, which confirms that the discrepancy really comes from 3D-mask effect.
Overlay (O/L) misalignment (M/A) is induced from numerous sources including metrology error and stage control error,
and aberration in projection optics. However, as design rule become smaller, aberration induced O/L M/A is evaluated to
take considerable portion in the overlay budget. This paper focuses on O/L M/A issues from projection optics. We
presents a simulation analysis of M/A between contact hole (C/H) pattern and line & space (L/S) pattern at 65nm node
based on the aberration data from actual lithography tool to single out the main source of O/L M/A.. The study shows
that the aberration in projection optics can induce considerable M/A and the conventional overlay keys do not represent
this M/A properly. Among the Zernike fringe polynomials, the third-order behavior (D3) in Z2 (tilt) is found to be the
critical source of misalignment. This portion of the aberration is resulted from the lens heating (LH) and can be corrected.
However, this correction method needs improvements because its controllability over LH is not enough for the complete
correction of LH induced M/A. Besides D3, Z10 (3-Foil) are found to be the major sources for pattern shift in C/H
patterns, and Z7 and Z14 (Coma x) are found for L/S patterns.
Many issues need to be resolved for a production-worthy model based assist feature
insertion flow for single and double exposure patterning process to extend low k1 process
at 193 nm immersion technology. Model based assist feature insertion is not trivial to
implement either for single and double exposure patterning compared to rule based
methods. As shown in Fig. 1, pixel based mask inversion technology in itself has
difficulties in mask writing and inspection although it presents as one of key technology to
extend single exposure for contact layer. Thus far, inversion technology is tried as a cooptimization
of target mask to simultaneously generate optimized main and sub-resolution
assists features for a desired process window. Alternatively, its technology can also be
used to optimize for a target feature after an assist feature types are inserted in order to
simplify the mask complexity. Simplification of inversion mask is one of major issue
with applying inversion technology to device development even if a smaller mask feature
can be fabricated since the mask writing time is also a major factor. As shown in Figure 2,
mask writing time may be a limiting factor in determining whether or not an inversion
solution is viable. It can be reasoned that increased number of shot counts relates to
increase in margin for inversion methodology. On the other hand, there is a limit on how
complex a mask can be in order to be production worthy. There is also source and mask
co-optimization which influences the final mask patterns and assist feature sizes and
positions for a given target. In this study, we will discuss assist feature insertion methods
for sub 40-nm technology.
Several criteria are applied to optimize the best illumination and bias condition for a layer. Normalized image log-slope
(NILS) and mask error enhancement factor (MEEF) are promising candidates to simply decide the optimized condition.
NILS represents imaging capability and MEEF represents the mask uniformity influence on wafer image. MEEF has
inversely relationship with NILS, but the optimized point of NILS does not exactly coincide with that of MEEF. Besides
NILS and MEEF, the depth of focus (DoF) is an important factor for defining the process margin. The process window
(PW) is expressed by DoF and exposure Latitude (EL). PW is general parameter used to determine the best lithographic
condition. Large EL can be obtained at the condition with good image performance. In order to include mask uniformity
effect in PW analysis, the common PW overlapping the final layout with positive and negative biased layouts is adopted.
Starting with the minimum NA, sigma and threshold, OPC is performed to satisfy the target layout using aerial image
model, and the final OPCed layout is obtained. The positive and negative biased layouts are generated from the final
OPCed layout. The bias limit is determined considering mask uniformity. The common PW obtained by overlapping the
final layout with positive and negative biased layouts is calculated. Then, NA, sigma and threshold are increased until
the maximum values are reached. The common PW at each NA, sigma and threshold value is obtained using the same
flow sequence. Comparing among calculated PWs, the NA, sigma and threshold of the maximum PW can be chosen as
the best illuminator and bias condition. In this paper, the optimized illumination and bias condition is determined using
PW for 60 nm memory device. The process flow is implemented by an OPC tool. By using the OPC tool for the
illuminator optimization, the actual layout and multiple monitoring points can be measured. In spite of a large number of
calculations, the fast calculation speed can be obtained by using the distributed process.
A new framework has been developed to model 3D thick mask effects for full-chip OPC and verifications. In addition to
electromagnetic (EM) scattering effects, the new model also takes into account the non-Hopkins oblique incidence
effects commonly found in real lithography systems but missing in prior arts. Evaluations against rigorous simulations
and experimental data showed the new model provides improved accuracy, compared to both the thin-mask model and
the thick-mask model based on Hopkins treatment of oblique incidence.
We present simplified symmetric boundary layer model (BLM) for Optical Proximity Correction (OPC) in order to account for thick (or 3D or topographic) mask effect. In this approach, near-field mask image which is quite different from original mask pattern due to mask topography is approximated as the original pattern and boundary layer around it. In this work, the boundary layer is determined as such that residual critical dimension (CD) error between measured CD and modeled CD from the BLM is minimized for various types of features. In case of sub-50 nm memory patterning, this BLM shows sufficient accuracy that root mean square of the residual CD is as small as 4.3 nm. Also, OPC speed with BLM is reasonably fast as the OPC time with BLM increases as only around twice as the conventional OPC time without BLM, which is acceptable in practice.
The specification of the mask mean-to-target (MTT) and uniformity is related to functions as: mask error enhancement
factor, dose sensitivity and critical dimension (CD) tolerances. The mask MTT shows a trade-off relationship with the
uniformity. Simulations for the mask MTT and uniformity (M-U) are performed for LOGIC devices of 45 and 37 nm nodes
according to mask type, illumination condition and illuminator polarization state. CD tolerances and after develop inspection
(ADI) target CD's in the simulation are taken from the 2004 ITRS roadmap. The simulation results allow for much smaller
tolerances in the uniformity and larger offsets in the MTT than the values as given in the ITRS table. Using the parameters
in the ITRS table, the mask uniformity contributes to nearly 95% of total CDU budget for the 45 nm node, and is even larger
than the CDU specification of the ITRS for the 37 nm node. We also compared the simulation requirements with the current
mask making capabilities. The current mask manufacturing status of the mask uniformity is barely acceptable for the 45 nm
node, but requires process improvements towards future nodes. In particular, for the 37 nm node, polarized illumination is
necessary to meet the ITRS requirements. The current mask linearity deviates for pitches smaller than 300 nm, which is not
acceptable even for the 45 nm node. More efforts on the proximity correction method are required to improve the linearity
Dummy contact generation procedure to apply off-axis illumination (OAI) to a contact layer in a 60 nm node device is described. The model based optical proximity correction (OPC) is also adopted to control the on-chip variation (OCV). The dummy contact size of 110 nm with the space distance of 90 nm between the main and dummy contact is used. By applying OPCed contact, the proximity variation is reduced less than 11 nm from 49 nm. The modeling methods are assessed by comparing delta edge placement error (EPE) values, which represent the model accuracy. The VTR_E model is shown to well correct the proximity variation, and it is adopted in our experiment.
Applying to the arbitrary patterns of logic device and to generate more dummy patterns, the rule needs to be modified. The modified rule includes the dummy merge method, and the dummy contacts are automatically generated for the contact layer of 60 nm node logic device.
The on-chip variation (OCV) should be critically controlled to obtain the high speed performance in logic devices. The variation from proximity dominantly contributes to OCV. This proximity effect can be compensated by applying well-treated optical proximity correction (OPC). Therefore, the accuracy of OPC is needed, and methods to enhance its result have to be devised. The optical proximity behaviors are severely varied according to the material and optical conditions. In point of material, the proximity property is affected by species of photo-resist (PR) and change of post exposure bake (PEB) conditions. 3σ values of proximity variation are changed from 9.3 nm to 15.2 nm according to PR species. Also, proximity variations change from 16.2 nm to 13.8 nm is observed according to PEB condition. Proximity variations changes of 11.6 nm and 15.2 nm are measured by changing the illumination condition. In order not to seriously deteriorate OPC, these factors should be fixed after the OPC rules are extracted. Proximity variations of 11.4 nm, 13.9 nm and 15.2 nm are observed for the mask mean-to-targets (MTT) of 0 nm, 2nm, and 4nm, respectively. The decrease the OPC grid size enhances the correction resolution and the OCV is reduced. The selective bias rule is generated by model using grid size of 1 nm and 0.5 nm. For the nominal CD of 87 nm, proximity variations are measured to be 14.6 nm and 11.4 nm for 1 nm and 0.5 nm grid sizes, respectively. The enhancement amount of proximity variations are 9.2 nm corresponding to 39% improvement. The CD uniformity improvement for adopting the small grid size is confirmed by measuring the CD uniformity on real SRAM pattern. CD uniformities are measured 11nm and 9.1nm for grid size of 1 nm and 0.5 nm, respectively. 22% improvement of the CD uniformity is achieved.
The introduction of ArF lithography technology is needed for on-chip linewidth variation(OCV) control less than 10nm in 90nm logic transistor development. Since conventional KrF lithography increased the burdens of mask fabrication and photo process due to excessive optical proximity correction(OPC), ArF lithography is more required to improve pattern feasibility in terms of line edge roughness(LER), corner rounding and contact overlapping margin than before. In this paper, we investigated two major components of OCV, that is, proximity and uniformity using ArF lithography. For a tighter CD control, the proximity can be corrected by hybrid OPC method, which is a combination of rule-based and model-based OPC. The uniformity can be effectively improved by several methods such as lithography-friendly layout formation, optimal substrate condition, decrease in MEEF and tuning of the resist process. In conclusion, by using ArF lithography we could obtain the satisfactory OCV control less than 10nm and reasonable process latitude simultaneously for 90nm logic gate under the condition of well-controlled proximity and uniformity.
For nonzero mean-to-target (MTT), critical dimension (CD) recovery to the nominal CD in the reference region by simply changing the dose cannot be achieved in the other regions with different pattern densities. The mask error enhancement factor (MEEF) and the exposure latitude (EL) depend on the pattern density, which cause the final CD mismatched to the nominal CDs. The formulaic expression of the mask margin for the MTT and uniformity is constructed as a function of the MEEF, the EL, and the nominal CD tolerance.
Line and space (L/S) pattern of 200 nm pitch size and isolated space pattern of 120 nm are designed and chosen as dense and sparse patterns, respectively. Simulation is performed using Gaussian convolution method, and the diffusion length is found to be 40 nm by fitting it to the measured data. The designed L/S pattern and isolated space pattern are exposed on chrome-on-glass mask using ArF scanner with 0.75NA and annular illuminating condition. The nominal CDs of L/S and isolated space pattern are 105 nm and 115 nm, respectively. The MEEF and the EL are measured to be 2.45 and 6.6 nm-cm2/mJ for L/S Pattern, and 1.86 and 8.60 nm nm-cm2/mJ for isolated space pattern, respectively. The summation values of the MTT and uniformity are calculated to be 8.6 nm with the tolerance of 5 nm for both patterns, and 6.7 nm with the tolerance of 3 nm for L/S pattern and 5 nm for isolated space pattern.
The mask margin for the MTT and uniformity proves to be changed for the variation of the nominal CD, or the feature size with the nominal CD fixed. By properly optimizing the conditions of illumination condition, mask type to be sued, and the feature size, the allowable mask tolerance for the MTT and uniformity could be increased.
As the design rule is rapidly decreased, tighter critical dimension (CD) control is highly requested. Considering the mask error enchantment factor, higher mask quality below 8nm should be guaranteed for 0.10micrometers generation devices. Among a number of actors causing CD errors in e-beam mask fabrication, dry etching plays an important role. Therefore, it is necessary to reduce loading effect for accurate CD control. As the loading effect in the dry etching is closely related to the selectivity of Cr to resist, a clue to reduce the loading effect is to reduce loading. In this paper, we will clarify the relation mechanism between the selectivity and loading effect. We will investigate the degree of loading effect by quantifying the selectivity with different etch processes.
A double exposure using mutually one-pitch-step shifted alt. PSM's is proposed to eliminate the LICD and CD reversal. By doubly exposing mutually one-pitch-step shifted alt. PSM's, the LICD and CD reversal is observed to disappear. The phase and undercut margins of 8° and 40 nm are observed, respectively by simulation for 1 .2 jim DOF margin. The alignment tolerance is calculated to be 75 nm which is enough for considerring recent lithographic systems. By doubly exposing mutually one-pitch-step shifted alt. PSM, almost identical CD's of 141 nm and 142 nm are measured. The phase margin of 15 0 (from 169° to 184°) and the undercut margin of 50 nm (from 100 nm to 150 nm) are observed for DOF margin of 1.0 rim. Our double exposing technique prove to have advantages over alt. PSM not only in removal of LICD and CD reversal, but also in the phase and undercut margin.
Double exposure using mutually one-pitch-step shifted alt. PSM's is proposed to eliminate the (Delta) CD and CD reversal. By doubly exposing mutually one-pitch-step shifted alt. PSM's, the (Delta) CD and CD reversal is observed to disappear. The phase margin of 8 degree(s) and the undercut margin of 40 nm are obtained for 1.2 micrometers DOF margin. Comparing with alt. PSM, double exposure using mutually one-pitch-step shifted alt. PSM has larger margin in undercut and phase, which allows mask to be manufactured easily. The alignment tolerance is calculated to be 75 nm which is enough compared with recent lithographic systems. By doubly exposing mutually one-pitch-step shifted alt. PSM, the equal CD's of 141 nm and 142 nm were observed. Our double exposing technique proved to have large advantages over alt. PSM not only in removal of (Delta) CD and CD reversal, but also in the phase and undercut margin.