Mr. Sunkeun Ji Profile

Sunkeun Ji

at SK Hynix Inc

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Publications (4)

Proceedings Article | 24 March 2016 Paper

Enhacement of intrafield overlay using a design based metrology system

Gyoyeon Jo, Sunkeun Ji, Shinyoung Kim, Hyunwoo Kang, Minwoo Park, Sangwoo Kim, Jungchan Kim, Chanha Park, Hyunjo Yang, Kotaro Maruyama, Byungjun Park

Proceedings Volume 9778, 97781J (2016) https://doi.org/10.1117/12.2218937

KEYWORDS: Overlay metrology, Metrology, Optical testing, Defect inspection, Inspection, Defect detection, Control systems, Semiconductors, Databases, Distortion, Chemical mechanical planarization, Etching

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Proceedings Article | 19 March 2015 Paper

Advanced overlay analysis through design based metrology

Sunkeun Ji, Gyun Yoo, Gyoyeon Jo, Hyunwoo Kang, Minwoo Park, Jungchan Kim, Chanha Park, Hyunjo Yang, Donggyu Yim, Kotaro Maruyama, Byungjun Park, Masahiro Yamamoto

Proceedings Volume 9424, 942415 (2015) https://doi.org/10.1117/12.2085464

KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Data analysis, Etching, Optical lithography, Double patterning technology, Imaging systems, Error analysis, Distortion

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Proceedings Article | 2 April 2014 Paper

Real cell overlay measurement through design based metrology

Gyun Yoo, Jungchan Kim, Chanha Park, Taehyeong Lee, Sunkeun Ji, Gyoyeon Jo, Hyunjo Yang, Donggyu Yim, Masahiro Yamamoto, Kotaro Maruyama, Byungjun Park

Proceedings Volume 9050, 90501O (2014) https://doi.org/10.1117/12.2046294

KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Computer aided design, Manufacturing, Inspection, Scanning electron microscopy, Image processing, Data processing, Metals

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Until recent device nodes, lithography has been struggling to improve its resolution limit. Even though next generation lithography technology is now facing various difficulties, several innovative resolution enhancement technologies, based on 193nm wavelength, were introduced and implemented to keep the trend of device scaling. Scanner makers keep developing state-of-the-art exposure system which guarantees higher productivity and meets a more aggressive overlay specification. “The scaling reduction of the overlay error has been a simple matter of the capability of exposure tools. However, it is clear that the scanner contributions may no longer be the majority component in total overlay performance. The ability to control correctable overlay components is paramount to achieve the desired performance.(2)” In a manufacturing fab, the overlay error, determined by a conventional overlay measurement: by using an overlay mark based on IBO and DBO, often does not represent the physical placement error in the cell area of a memory device. The mismatch may arise from the size or pitch difference between the overlay mark and the cell pattern. Pattern distortion, caused by etching or CMP, also can be a source of the mismatch. Therefore, the requirement of a direct overlay measurement in the cell pattern gradually increases in the manufacturing field, and also in the development level. In order to overcome the mismatch between conventional overlay measurement and the real placement error of layer to layer in the cell area of a memory device, we suggest an alternative overlay measurement method utilizing by design, based metrology tool. A basic concept of this method is shown in figure1. A CD-SEM measurement of the overlay error between layer 1 and 2 could be the ideal method but it takes too long time to extract a lot of data from wafer level. An E-beam based DBM tool provides high speed to cover the whole wafer with high repeatability. It is enabled by using the design as a reference for overlay measurement and a high speed scan system. In this paper, we have demonstrated that direct overlay measurement in the cell area can distinguish the mismatch exactly, instead of using overlay mark. This experiment was carried out for several critical layer in DRAM and Flash memory, using DBM(Design Based Metrology) tool, NGR2170™.

Proceedings Article | 18 April 2013 Paper

Application of DBM tool for detection of EUV mask defect

Gyun Yoo, Jungchan Kim, Chanha Park, Taehyeong Lee, Sunkeun Ji, Hyunjo Yang, Donggyu Yim, Byeongjun Park, Kotaro Maruyama, Masahiro Yamamoto

Proceedings Volume 8681, 868121 (2013) https://doi.org/10.1117/12.2011476

KEYWORDS: Photomasks, Inspection, Wafer inspection, Semiconducting wafers, Metals, Extreme ultraviolet, Extreme ultraviolet lithography, Metrology, Defect inspection, Lithography

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