In recent years, CCD-in-CMOS TDI image sensors are becoming increasingly popular for many small satellite missions to assure a fast and affordable access to space for Low Earth Observation. Our monolithic CCD-inCMOS TDI imager features a specifically developed technology which combines the benefits of a classical CCD TDI with the advantages of CMOS System-On-a-Chip (SoC) design. Like CCD, this detector is also controlled by a large number of clock voltages. Optimizing these voltages allows to increase the performance of the detector by improving multiple characteristic parameters, such as full well capacity (FWC), dark current, linearity, dark signal non-uniformity (DSNU) and charge transfer efficiency (CTE). Traditionally, it has been the standard practice to adjust the CCD voltages by trial and error methods to get a better image. Because of the large parameter space, such subjective procedures may yield far from the optimum performance. This paper reports a design of experiments (DOE) technique applied on the clock voltages to improve the multiple performance parameters of the detector. This method utilizes the Taguchi’s orthogonal arrays of experiments to reduce the number of experiments with different voltage combinations. Finally, optimal combination of clock voltages is obtained by converting the multiple performance parameters of the detector into a single Grey relational grade. In this process, the sequences of obtaining parameter values are categorized according to the performance characteristics. The condition Higher-the-better is used for parameters like FWC and CTE whereas condition Lower-the-better is applied for parameters, such as dark current, linearity error and DSNU.
In past decade, CMOS imagers are becoming increasingly popular in scientific imaging like astronomy. Large format image sensors are the detector of choice for the wide field imaging. The circuit integration capability of the CMOS imager is considered as an advantage while inducing the temperature variation over the sensor area. Dark current of the image sensor is strongly temperature-dependent signal and one of the limiting factors of the low light imaging. Here, we present per-pixel dark current measurement results and analysis of a 7638 x 5004 pixels front-side illuminated CMOS image sensor with a pixel pitch of 6 μm. In this work, global non- uniformity induced by the on-chip temperature variation is controlled by the Peltier junction device. This paper reports results of our dark current study for the temperature range 233 to 273 K with exposure of 0 to 300 s. A reasonably low dark current of 0.014 e-/pixel/s is achieved at 233 K temperature. The dark current spatial distributions at different temperatures are presented. We extracted the activation energy for the dark current in this lower temperature range. Using the Arrhenius law, dark current data analysis shows the Meyer-Neldel Relationship (MNR) between the Arrhenius pre-factor and the apparent activation energy.
We are characterizing a 7638 x 5004 front-side illuminated CMOS detector for astronomical application. Mod- ulation Transfer Function (MTF) of a detector is considered as an important figure of merit for accurate target positioning in astronomy. It states the upper limit of the image quality. MTF knowledge also provides a better understanding of the design trade-off. In this work, two-dimensional (2D) sub-micrometer scanning method is used to extract 2D MTF profile of our CMOS detector with a pixel pitch of 6μm. Our optical measurement setup focuses a collimated beam onto the imaging surface with a microscope objective. The spot was scanned in a raster over a single pixel. We generate an oversampled point spread function (PSF) of the detector which contains sub-pixel elements. 2D MTF map is calculated from the measured oversampled PSF. This 2D MTF map is used to characterize the resolving ability of our detector. We analyze the importance of the 2D MTF map to describe the full pixel MTF of the CMOS pixel having low fill-factor. 1D MTFs are calculated from the 2d MTF to do a quantitative comparison of the MTF in horizontal and vertical directions. This study emphasizes advantages and necessity of the 2D MTF for CMOS detector performance analysis, especially for anisotropic resolution.
Inter-pixel crosstalk degrades the point spread function (PSF) of a scientific imager which affects quantitative interpretation of scientific image data. Compared to the CCD, crosstalk is larger in the CMOS image sensor. This problem is challenging due to constant downscaling of the CMOS technology and pixel size. In this work, we parametrized the inter-pixel crosstalk and also modeled it as an empirically quantifiable kernel. A CMOS image sensor with 6 μm pixel pitch is measured. Evidently the crosstalk value can change with the PSF centroid position inside a pixel, primarily due to the spatial extent of the beam, which causes some optical generation in the surrounding pixels. We demonstrate a crosstalk measurement method and its spatial variation with respect to the spot position. This sub-pixel scanning is conducted to measure any crosstalk variation with respect to the sub-pixel spot position. Notable asymmetry on the crosstalk value between rows and columns as well as in the four corners of the POI is observed. This variation shows how the signal is shared at the pixel boundaries. Several POIs (Pixel of interest) over the scan region are measured to analyze the crosstalk variations.
CMOS imagers are becoming increasingly popular in astronomy. A very low noise level is required to observe extremely faint targets and to get high-precision flux measurements. Although CMOS technology offers many advantages over CCDs, a major bottleneck is still the read noise. To move from an industrial CMOS sensor to one suitable for scientific applications, an improved design that optimizes the noise level is essential. Here, we study the 1/f and thermal noise performance of the source follower (SF) of a CMOS pixel in detail. We identify the relevant design parameters, and analytically study their impact on the noise level using the BSIM3v3 noise model with an enhanced model of gate capacitance. Our detailed analysis shows that the dependence of the 1/f noise on the geometrical size of the source follower is not limited to minimum channel length, compared to the classical approach to achieve the minimum 1/f noise. We derive the optimal gate dimensions (the width and the length) of the source follower that minimize the 1/f noise, and validate our results using numerical simulations. By considering the thermal noise or white noise along with 1/f noise, the total input noise of the source follower depends on the capacitor ratio CG/CFD and the drain current (Id). Here, CG is the total gate capacitance of the source follower and CFD is the total floating diffusion capacitor at the input of the source follower. We demonstrate that the optimum gate capacitance (CG) depends on the chosen bias current but ranges from CFD/3 to CFD to achieve the minimum total noise of the source follower. Numerical calculation and circuit simulation with 180nm CMOS technology are performed to validate our results.