In this paper, we will discuss patterning challenges of EUV lithography to apply 1xnm node DRAM. EUV lithography is
positioned on essential stage because development stage for DRAM is going down sub-20nm technology node. It is time to decide how to make sub-20nm node DRAM. It will be the simplest and cost effective way to make device with
matured EUVL. But in spite of world-wide effort to develop EUV lithography, the maturity of EUV technology is still
lower than conventional ArF immersion lithography. So, DRAM manufacturers are considering several candidates such
as DSA, DPT and MPT simultaneously. In addition, DRAM manufacturers are considering new cell layout and new
memory also. For this study, we investigate process window and shadow effect across exposure field of sub-20nm node DRAM cell. We also performed an overlay matching experiment between 0.25NA EUV scanner and 1.35NA ArF
immersion scanner. In addition, we will compare EUV lithography with ArF immersion DPT or SPT in view of patterning performance. Finally, we will discuss some technical issues to applying EUV lithography such as flare, resist LER, EUV OPC and illumination condition using 0.25NA EUV scanner.
In recent years, DRAM technology node has shrunk below to 40nm HP (Half Pitch) patterning with significant
progresses of hyper NA (Numerical Aperture) immersion lithography system and process development. Especially, the
development of DPT (Double Patterning Technology) and SPT (Spacer Patterning Technology) can extend the resolution
limit of lithography to sub 30nm HP patterning. However it is also necessary to improve the tighter overlay control for
developing the sub 40nm DRAM because of small device overlap margin. Since new process technologies such as
complex structure of DPT and SPT, new hard mask material and extreme CMP (Chemical Mechanical Planarization)
process have also applied as design rule is decreased, the improvement of process overlay control is very important.
In this paper, we have studied that the characterization of overlay performance for sub 40nm DRAM with actual
experimental data. First, we have investigated the influence on the intra field overlay and inter field overlay with
comparison of HOWA and HOPC and the improvement of inter field overlay residual errors. Then we have studied the
process effects such as hard mask material, thermal process and CMP process that affect to overlay control.
In this paper, we will present applications of MoSi-based binary intensity mask for sub-40nm DRAM with hyper-NA
immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for
polarized illumination and mask materials in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of
binary intensity mask are used for this experiment; those are ArF att.PSM ( MoSi:760Å , transmittance 6% ),
conventional Cr ( 1030Å ) BIM (Binary Intensity Mask), MoSi-based BIM ( MoSi:590Å , transmittance 0.1%) and multi
layer ( Cr:740Å / MoSi:930Å ) BIM. Simulation and experiment with 1.35NA immersion scanner are performed to study
influence of mask structure, process margin and effect of polarization. Two types of DRAM cell patterns are studied; one
is a line and space pattern and the other is a contact hole pattern through mask structure. Various line and space pattern is
also through 38nm to 50nm half pitch studied for this experiment. Lithography simulation is done by in-house tool based
on diffused aerial image model. EM-SUITE is also used in order to study the influence of mask structure and
polarization effect through rigorous EMF simulation. Transmission and polarization effects of zero and the first
diffraction orders are simulated for both att.PSM and BIM. First and zero diffraction order polarization are shown to be
influenced by the structure of masking film. As pattern size on mask decreases to the level of exposure wavelength,
incident light will interact with mask pattern, thereby transmittance changes for mask structure. Optimum mask bias is
one of the important factors for lithographic performance. In the case of att.PSM, negative bias shows higher image
contrast than positive one, but in the case of binary intensity mask, positive bias shows better performance than negative
one. This is caused by balance of amplitude between first diffraction order and zero diffraction order light.1
Process windows and mask error enhancement factors are measured with respect to several types of mask structure. In
the case of one dimensional line and space pattern, MoSi-based BIM and conventional Cr BIM show the best
performance through various pitches. But in the case of hole DRAM cell pattern, it is difficult to find out the advantage
of BIM except of exposure energy difference. Finally, it was observed that MoSi-based binary intensity mask for sub-
40nm DRAM has advantage for one dimensional line and space pattern.
In the field of lithography technology, EUV lithography can be a leading candidate for sub-30 nm technology node.
EUVL expose system has different characteristics compared to DUV exposure system. EUV source wavelength is short
and no material is transparent to the source. So off-axis reflective optic system is used for patterning in place of on-axis
refractive system of DUV system. And different reticle design is needed that consists of 40 pair of Mo/Si multi layer
and absorber layer in place of conventional mask. Because of the oblique incidence on the mask, shadowing effect is
occurred such as pattern asymmetry, shift and pattern bias depending on pattern orientation. For non-telecentric
characteristics of EUV scanner, shadowing effect produces CD variation versus field position. Besides, it is well
known that EUV scanner has bigger flare than conventional DUV scanner. Therefore, the correction of mask shadowing
effect and flare level are one of the important issues for EUV lithography.
In this paper, process window and MEF of EUV lithography has been examined by 3D mask simulation. CD
variation by shadowing is simulated for various pattern orientations. A shadowing correction method has been
calculated due to field position to reduce shadowing effect. And the correction effect is examined by simulation and
Experimental results. Principle of radial overlay shift due to field position is verified then the shift length of line and
space pattern is calculated.
In this paper, we will present comparison of DRAM cell patterning between ArF immersion and EUV lithography which
will be the main stream of DRAM lithography. Assuming that the limit of ArF immersion single patterning is around
40nm half pitch, EUV technology is positioned on essential stage because development stage of device manufacturer is
going down sub-40nm technology node. Currently lithography technology, in order to improve the limitation of ArF
immersion lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been
examined intensively. However, double patterning and spacer patterning technology are not cost-effective process
because of complexity of lithography process such as many hard mask stacks and iterative litho, etch process. Therefore,
lithography community is looking forward to improving maturity of EUVL technology.
In order to overcome several issues on EUV technology, many studies are needed for device application. EUV
technology is different characteristics with conventional optical lithography which are non-telecentricity and mask
topography effect on printing performance. The printed feature of EUV is shifted and biased on the wafer because of
oblique illumination of the mask. Consequently, target CD and pattern position are changed in accordance with pattern
direction, pattern type and slit position of target pattern.1
For this study, we make sub-40nm DRAM mask for ArF immersion and EUV lithography. ArF attenuated PSM (Phase
Shift Mask) and EUV mask (LTEM) are used for this experiment; those are made and developed by in-house captive
maskshop. Simulation and experiment with 1.35NA ArF immersion scanner and 0.25NA EUV full field scanner are
performed to characterize EUV lithography and to compare process margin of each DRAM cell. Two types of DRAM
cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node pattern with
contact hole shape. Line and space pattern is also studied through 24nm to 50nm half pitch for this experiment.
Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE and Solid-EUV are
also used in order to study characteristics of EUV patterning through rigorous EMF simulation. We also investigated
shadowing effect according to pattern shape and design rule respectively. We find that vertical to horizontal bias is
around 2nm on 32nm to 40nm half pitch line and space pattern. In the case of DRAM cell, we also find same result with
line and space pattern. In view of mask-making consideration, we optimize absorber etch process. So we acquire vertical
absorber profile and mask MTT(Mean To Target) within 10% of target CD through several pitch.
Process windows and mask error enhancement factors are measured with respect to several DRAM cell pattern. In the
case of one dimensional line and space and two dimensional brick wall pattern, vertical pattern shows the best
performance through various pitches because of lower shadowing effect than horizontal pattern. But in case of contact hole DRAM cell pattern such as storage node pattern, it has bigger MEF value than one or two dimensional pattern
because of independency of shadowing effect. Finally, we compare with 2x, 3x and 4x DRAM cell patterning
performance in terms of pattern fidelity, slit CD uniformity and shadowing effect.
In recent years, DRAM and Flash technology node has shrunk below to 45nm half pitch (HP) patterning with significant progresses of hyper numerical aperture (NA) immersion lithography system and process development. Several technologies such as extreme ultra violet (EUV) lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been developed for sub 40nm HP device. High index immersion lithography (HIL) is also one of the candidates for next generation lithography technology that has benefits of product cost, process simplification and usage for existing infrastructure though this technology must overcome critical issues--high index immersion fluid and lens optic development.
In this paper, we will present simulation results on sub 40nm imaging characterization for HIL.
First, we have studied the image performance for sub 40nm patterning with HIL. The image contrast, optical proximity effect and mask error enhanced factor (MEEF) are investigated through simulation. As pattern size decrease and lens NA gets bigger and bigger, the features on mask get smaller even below the wavelength of light and polarization related effects become one of the most critical issues. From comparison with results for 45nm HP patterning, we are able to suggest the reasonable process condition for HIL process.
Then, we have investigated the optimum BARC condition to make preparations for 32nm HP pattering.
New concepts about transistor structure are being introduced for sub-50nm memory products. As the memory cell
design is shrinking down, conventional transistor of planar structure can not guarantee safe transistor operation.
Newly introduced transistor has to ensure robust transistor operation characteristics and process stability
simultaneously. One of the candidates which are being developed recently is vertical transistor. The basic layout to
integrate vertical transistor include very dense 2-dimensional features. The new memory cell based on dense structure
can also contribute to reduction of cell area compared to conventional memory cell such as 8F2 planar cell. While new
memory structure enables the reduction of chip size, its 2-dimensional structure limits resolving performance of optical
lithography inevitably. It is very challenging to build 4F2 dense features of sub-50nm node by single exposure
technology using hyper NA ArF lithography before the EUV era. In this paper, the feasibility of 2-dimensional dense
structure at 50nm node is presented and various techniques are introduced to realize new memory scheme as next
generation memory cell structure.
In this paper, we will present comparison of attenuated phase shift mask and binary intensity mask at hyper-NA
immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for
polarized illumination in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of binary intensity mask
are used for this experiment; those are ArF att.PSM ( MoSi:Å ), thick Cr ( 1030Å ) BIM (Binary Intensity Mask),
thin Cr ( 590Å ) BIM and multi layer ( Cr:740Å / MoSi:930Å ) BIM. Simulation and experiment with 1.35NA
immersion scanner are performed to study influence of mask structure, process margin and effect of polarization. Two
types of DRAM cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node
pattern with contact hole shape. Line and space pattern is also studied through 38nm to 50nm half pitch for this
experiment. Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE is also
used in order to study the influence of mask structure and polarization effect through rigorous EMF simulation.
Transmission and polarization effects of zero and first diffraction order are simulated for both att.PSM and BIM. First
and zero diffraction order polarization are shown to be influenced by the structure of masking film. As pattern size on
mask decreases to the level of exposure wavelength, incident light will interact with mask pattern, and then transmittance
changes for mask structure. Optimum mask bias is one of the important factors for lithographic performance. In the case
of att.PSM, negative bias shows higher image contrast than positive one, but in case of binary intensity mask, positive
bias shows better performance than negative one. This is caused by balance of amplitude between first diffraction order
and zero diffraction order light.
Process windows and mask error enhancement factors are measured with respect to various design rules, i.e., different k1
levels at fixed NA. In the case of one dimensional line and space pattern, thick Cr BIM shows the best performance
through various pitches. But in case of two dimensional DRAM cell pattern, it is difficult to find out the advantage of
BIM for sub-45nm. It needs further study for two dimensional patterns. Finally, it was observed that thick Cr binary
intensity mask for sub-45nm has advantage for one dimensional line and space pattern.
In this paper, we will present experimental results on 45nm node patterning of DRAM and some technical issues for
polarized illumination in hyper NA imaging. First, practical k1 limit of 1.2NA ArF immersion system is investigated
through experiment. Process window and mask error enhancement factors are measured with respect to various design
rules, i.e., different k1 levels at fixed NA. Reasonable process window and MEEF value of around 3 are achieved in
DRAM gate and isolation layers at around 0.28 k1 regime. It is obvious that feasibility of this lowered k1 was realized
by the help of polarized illumination when we compared the results with that of 60nm patterning at 0.93NA tool -
corresponding k1 is 0.29 - without polarized illumination. Then consideration about degree of polarization state must
come next to the benefit of polarized illumination. Input polarization state is changed by birefringence of lens or mask
materials but it is very difficult to correlate the birefringence level and critical dimension of patterns experimentally.
Double exposing method was contrived to measure the effect of degree of polarization on DICD. And we also measure
the polarization dependent transmittance of light on mask by using 1.2NA immersion scanner. As a result, birefringence
and mask feature interaction with light seems not to be a serious issue for 45nm hyper NA polarized imaging.
Though speculation on immersion is ignited by the possibility in realization of hyper NA lithography system which will have NA> 1.0, it is thought that the immersion era might come earlier even in ≤1.0 NA regime because of great benefit in increasing DOF. On the other hand, questions are still laid on maturity or reliability issues such as lens contamination, bubble defects, overlay control and so forth. The main subject of this paper is how to find the appropriate time for introduction of immersion. Basic performance of immersion lithography in 80nm DRAM is compared with that of conventional dry lithography through experiment and simulation. Result of simulation is quite well matched with that of the experiment, and therefore we can investigate the limit of conventional dry lithography based on the simulation results.60nm node might be remained as a last regime for conventional dry lithography by virtue of polarized illumination, and we can expect the shoreline beyond there.
512Mbit DRAM with 70 nm design rule was tailored using 0.31k1 ArF lithography technologies. Of the critical mask layers, four pattern layouts were demonstrated: brick wall, line/space, contact and line/contact patterns. For the sake of cost reduction, the conventional technologies were used. Results has shown that SLR (Single-Layer Resist) process, half-tone PSM and the conventional illuminations had a potential of manufacturing 70 nm DRAM. However, it was found that brick wall patterns had asymmetrical shape and total CD uniformity was out of target raging 9.2 nm through 16.3 nm depending mask layouts. We prospect that higher contrast resist and more elaborate resist process will address these problems sooner or later. In case the immersion lithography is not ready around the right time, the feasibility of 0.29k1 ArF lithography was studied through simulation and test, which represented that 0.29k1 technologies were likely to be applied for the development of 60 nm DRAM with the aid of RETs (Resolution Enhancement Technologies) including customized illumination and new hard mask process.
We have studied several factors having an effect on LER in terms of resist chemistry, resist process, CD-SEM metrology, numerical aperture and sigma settings of the exposure tool, and the mask pattern. LER is extracted from the developed resist profile. In ArF lithography process, development and rinse process is very critical because ArF resist is relatively hydrophobic compared to KrF resist. It causes heterogeneous interaction at interface of resist and aqueous solution (developer or deionized water). We improved roughness at contact hole pattern by the introduction of wetting process prior to development. Clear and homogeneous rinsing is also needed to remove scum and swelled resist generated at development step. On the other hand, the roughness of mask pattern is one of the important factors of LER on wafer. We confirmed that this global dislocation is a potent influence but local edge roughness of mask is insignificant to wafer LER. This dislocation of pattern is originated from the lack of shot accuracy in E-beam writer using variable shaped beam.
Various enhancement techniques such as alternating PSM, chrome-less phase lithography, double exposure, etc. have been considered as driving forces to lead the production k1 factor towards below 0.35. Among them, a layer specific optimization of illumination mode, so-called customized illumination technique receives deep attentions from lithographers recently. A new approach for illumination customization based on diffraction spectrum analysis is suggested in this paper. Illumination pupil is divided into various diffraction domains by comparing the similarity of the confined diffraction spectrum. Singular imaging property of individual diffraction domain makes it easier to build and understand the customized illumination shape. By comparing the goodness of image in each domain, it was possible to achieve the customized shape of illumination. With the help from this technique, it was found that the layout change would not gives the change in the shape of customized illumination mode.
In this paper, we discuss feasibility of ArF chromeless mask (CLM) for sub-80nm era. Simulation and experiment are performed in terms of influence of quartz sidewall angle of CLM, process margin for 80nm DRAM cells, and mask polarity such as trench or mesa etc. Mask layouts are optimized through the use of resist patterning simulation for various critical layers of DRAM with trench and mesa type CLM, respectively. Lithography simulation is done by using in-house tool based on diffused aerial image model. SOLID-CTM is also using in order to study the influence of quartz sidewall angle and mask polarity. In the case of mask polarity, mesa type CLM is easier to make in the view of mask-making process, but in view of lithographic performance, trench type CLM is found to be better than mesa type. Quartz sidewall angle of CLM is one of the important factors for lithographic performance. The quartz sidewall angle of CLM gives severe impact on the lithographic performance. As quartz sidewall angle of CLM gets below 90 degrees, image quality, such as process window, aerial image contrast, are further degraded especially in the mesa type CLM. In addition, we also studied influence of phase error, transmittance error etc.
The purpose of this paper is to do the direct comparison of between the novel chrome-less phase shift mask (CLM), which is suggest by Chen et. al. recently, and attenuated phase shift mask which has been in the main stream of DRAM lithography. Our study is focused on the question of whether the CLM technology has a potential advantages compared with attenuated PSM, so as to substitute the position of it in 0.3 k1 lithography era of DRAM. Firstly, some basic characteristics of both masks are studied, that is intensity distribution of diffraction orders and optical proximity effect etc. And then mask layouts are optimized through the resist patterning simulation for various critical layers of DRAM with CLM and attenuated PSM, respectively. Resolution performances such as exposure latitude and DOF margin and mask error enhancing factor etc. are compared through the simulations and experiments. In addition, it is also studied in the point of mask manufacturing of CLM such as phase control issues, defect printability, mask polarity, and so forth.
In this paper, we will discuss the limitation of optical lithography with various resolution enhancement technologies. Lithography simulation was done by Hynix OPC Simulation Tool (HOST) based on Diffused Aerial Image Model (DAIM). The effects of numerical aperture (NA), wavelength, illumination conditions, mask and diffusion length of acid were simulated in view of resolution improvement. Diffusion length of acid is a dominant factor for resolution improvement for sub-100 nm era. As pattern size decreased, the limitation of optical lithography is more affected by diffusion length of acid. And other factors (NA, wavelength, illumination conditions and mask) will be discussed. Finally, ultimate the limitation of lithography will be discussed analytically.
We can print the contact hole pattern beyond the optical resolution limit using resist flow process. But its application has not strong point for the layer having various kinds of contact hole size and duty ratio according to x-axis or y-axis. Nevertheless, for the mass production of sub-150nm design rule device with KrF lithography using resist flow process, moderate shrink bias of below 40nm is required because the CD uniformity gets worse as the shrink bias gets larger by the influence of the hotplate dependency. We developed novel technology of shrinking contact hole using chemically amplified resist. It is generally known that the chemically amplified resist have t- top profile or larger line width when it has too much post exposure delay time at high amine concentration. Using this phenomenon, we intentionally treated amine of hexamethyl disilazane between exposure step and post exposure bake step, so we got smaller contact hole. Pattern profile of contact holes obtained by CONPEAT(CONtact hole resolution enhancement by Post Exposure Amine Treatment) process was fine. The contact size was 190nm with normal process and it was shrunk to 150nm using CONPEAT process. In this paper, we report the novel contact hole shrinkage technology of CONPEAT process. Its process feasibility was studied considering pattern fidelity, shrink bias and CD uniformity. We also introduce the experimental results of super contact hole shrinkage process using both contact hole shrinkage technology of CONPEAT process and resist flow process simultaneously.
In this paper, we will discuss feasibility of KrF and ArF technology to overcome 100 nm node. Simulation and experiment for this study were performed in view of mask error factor. Lithography simulation was done by Hyundai OPC Simulation Tool (HOST) based on diffused aerial image model (DAIM). In the case of k1 factor below 0.33, the photolithography process has no margin because of higher MEF value. Therefore, numerical aperture for KrF and ArF need to have over 0.95 and 0.75 respectively for 100 nm node. Actually, it is impossible to make exposure system with 0.95 NA. The mask error factor gave severe influence on the lithographic performance. To overcome 100 nm node, ArF lithography technology is more appropriate than KrF lithography considering MEF concept.
The patterning potentialities of sub-100nm pattern for ArF lithography was evaluated with conventional alternating PSM (alt-PSM) for dense lines and spaces (L/S) and phase edge PSM (PE-PSM) for isolated lines of memory device. In dense L/S pattern,110nm pattern was defined with relatively small depth of focus(DOF) window(~ 0.2 ?m) due to phase error of mask. As pattern sizes was changed from 130nm to 200nm, critical dimension (CD) difference between two neighboring spaces was varied and it was assumed that micro loading effect was occurred in Qz etching. The linearity was guaranteed to dense L/S of 110nm and isolated line of 90nm, and Iso-Dense bias was controlled within 15nm. The 60nm and 70nm isolated lines of PE-PSM ware defined with good process windows in the case of OA_X size(X-direction size of Cr open area) of 0.5 ?m. The 55nm isolated line was also defined. The pattern shift of isolated lines was occurred with 4~7nm as phase of mask was varies within 190 ~ 200 ° . Though the alt-PSM with high numerical aperture (NA) for ArF lithography was strong candidates for sub-1 OOnm lithography of memory device, the issues of mask fabrication such as tighter phase control and minimizing etch loading effect would be big obstacles. On the contrary, there were many possibilities of sub-100nm patterning in PE-PSM with good process windows, however tighter control of pattern shift due to phase error must be studied intensively.
Optical lithography at resolution limit is a non-linear pattern transfer. One of the important issue is a mask critical dimension control because of nonlinear amplification of mask critical dimension error during image transferring on wafer. This amplification of mask error is called the MEF. This mask error factor has been widely used as an important parameter for indicating tighter CD control for the photomask for low-kl lithography generation.
Photomask is one of the most critical technologies for lithography. Optical lithography at resolution limit is a non- linear pattern transfer process. OPC (Optical Proximity Correction) technology has been used in the semiconductor industry for controlling the shape of pattern, and eliminating the line shortening and corner rounding effects for submicron feature. Therefore, OPC technology is an approach for improving lithography performance that has been received much attention recently. We investigated the lithographic performance in terms of EL (Exposure Latitude), DOF (Depth of Focus), and mask error effects for various mask fabrication. It was observed that mask error gave severe influence on the lithographic performance and the OPC simulation error also strongly depended upon the mask quality.