Dr. Taekwon Jee Profile

Dr. Taekwon Jee

at SK Hynix, Inc.

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Author

Publications (4)

Proceedings Article | 10 April 2024 Presentation + Paper

Real time EPE measurement as a yield correlated metrology on advanced DRAM nodes

Taekwon Jee, Joonsang You, Hong-Goo Lee, Seungmo Hong, Jonghoi Cho, Taeseop Lee, Jong-hyun Seo, Michael Shifrin, Ronnie Porat, Amir Rosen, Rohit Kumar Singh, Jeong-Ho Yeo, Younghoon Kim, Jun Park, Byung-Jo Lim, Chan-Hee Kwak

Proceedings Volume 12955, 129550P (2024) https://doi.org/10.1117/12.3010813

KEYWORDS: Overlay metrology, Critical dimension metrology, Metrology, Semiconducting wafers, Stochastic processes, Time metrology, Design, Data modeling, Process control, Optical lithography

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The Edge Placement Error (EPE) is growing concerns due to the complexity increases of process variation as the design rule shrinkage of DRAM device. The EPE is a well-accepted metric which can be derived from CD, Overlay and LER measurements from more than patterning layers that concerned. Therefore, real time EPE measurement becomes a major factor to monitor and control the pattern fidelity. The pattern fidelity could be found from the edge placement measurement as a distance to design intent as possible without pattern defects. However, the traditional application of photolithography and etch biases according to a design rule or model for identifying pattern fidelity has inherent low TMU, multiple non consistence data sources and time-consuming off-line analysis. In previous works, we demonstrated the innovative e-Beam EPE metrology application using All-In-One (AIO) methodology to comply the required Total Measurement Uncertainty (TMU) and Time to Result (TTR) on the advanced DRAM nodes. AIO imaging and analysis methodology that deconvolute CD, overlay and relevant EPE metrics from a single see-through image is the most important differentiation for this EPE analysis approach. The in-cell direct EPE measurement with All-In-One (AIO) imaging and massive sampling demonstrates the better process controls and monitoring from the co-optimization of multiple control parameters and direct measurement of the yield relevant metrics. In this paper, we would like to show a couple of EPE monitoring use cases which shows good correlation to the final yield map through the massive and multi-layer measurements. Especially, it is expected that the EPE component which measures the edge-to-edge distance between different features of multi-layers can be a useful indicator for predicting yield along with CD and overlay. To investigate the local and random variabilities, which local stochastic effects are contained, we also studied the degree of yield prediction of the EPE component with increasing number of measurement sites in local area. It is proposed that using a large amount of measurement sites allows to improve the yield prediction accuracy to a certain extent, which means the local stochastic effects can be effectively analyzed with the use of massive metrology approach. In addition, from the prediction accuracy study using EPE model-based machine learning, we proved that the EPE is sufficiently sensitive indicator to capture potential yield-loss problems in normal wafer, as well. Therefore, in-line EPE monitoring using AIO metrology enables the root-cause analysis of patterning weak points and provides a better process monitoring/correction solution to enable faster advanced DRAM node development ramp and high-volume stability.

Proceedings Article | 27 April 2023 Poster + Paper

Large field of view metrology: detecting critical edge placement error signatures not seen with small field of view in an HVM environment

Mohamed Ridane, Ivy Chen, Jaden Song, Peter Nikolsky, Kuan-Ming Chen, Shinyeong Lee, Sean Park, Kolos Lin, Yu-Chi Su, Kyoyeon Cho, Ethan Yu, James Park, Abdalmohsen Elmalk, Chih-Hung Hsieh, Alexander Serebryakov, Lei Zhang, Taekwon Jee, Joonsang You, Hong-Goo Lee, Jongmin Park, Jungchan Kim, Sang-Woo Kim, Seungmo Hong, Jaewook Seo

Proceedings Volume 12496, 124963C (2023) https://doi.org/10.1117/12.2659692

KEYWORDS: Metrology, Semiconducting wafers, High volume manufacturing, Line width roughness, Critical dimension metrology, Scanning electron microscopy, Optical lithography, Environmental sensing, Edge detection, Overlay metrology

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Proceedings Article | 13 June 2022 Presentation

Evaluation of robust EPE monitoring and control metric methodologies for advanced DRAM nodes yield improvement

Yaniv Abramovitz, Jeong-Ho Yeo, Taekwon Jee, Hong-Goo Lee, Sang-Ho Lee, Chan-Ha Park

Proceedings Volume PC12053, PC120530N (2022) https://doi.org/10.1117/12.2613931

KEYWORDS: Overlay metrology, Image processing, Yield improvement, Metrology, Line edge roughness, Process control, Critical dimension metrology, Scanning electron microscopy, Optical lithography, Inspection

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Proceedings Article | 22 February 2021 Presentation + Paper

Edge placement error wafer mapping and investigation for improvement in advanced DRAM node

Kuan-Ming Chen, Wolfgang Henke, Ji-Hoon Jung, Ewa Kasperkiewicz, Anita Bouma, Rizvi Rahman, Gratiela Isai, Gwang-Gon Kim, Sotirios Tsiachris, Jae-Doug Yoo, Yuna Park, JaeYoung Park, Jonggeun Won, Nang-Lyeom Oh, Hsin-Yu Chen, WeiTai Lin, Chih-Hung Hsieh, Kuo-Feng Pao, Kyoyeon Cho, Abdalmohsen Elmalk, Sudharshanan Raghunathan, Taekwon Jee, Seung-Uk Jeong, Jeongwoo Jae, Sang-Woo Kim, Dongyoung Lee, Jungchan Kim, WonKwang Ma, Sang-Ho Lee, Chan-Ha Park

Proceedings Volume 11611, 116111V (2021) https://doi.org/10.1117/12.2584149

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Overlay metrology, Optical lithography, Metrology, Visualization, Statistical analysis, Lithography, Graphic design, Etching

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