Computational spacer patterning technology (SPT) has been developed for the first time to address the
challenges concerning hotspots and mask specifications in SPT. A simulation combined with a lithography, etching and
deposition model shows the strong correlation of 0.999, 0.993, 0.980 with the experimental critical dimension (CD),
mask error-enhancement factor (MEEF) and defect printability through a series of spacer processes, respectively.
Furthermore, a design for manufacturability (DfM) flow using computational SPT can find hotspots caused by spacer
patterning processes as well as those caused by lithography process and help designers make the circuit layout more
robust. Besides, a newly defined MEEF and defect printability, which are primary metrics for mask specification, can be
predicted so accurately by using computational SPT that the new scheme to determine appropriate mask specifications is
shown to be feasible under the spacer patterning process condition. Thus, computational SPT is found to be promising
for addressing the challenges concerning hotspot removal and mask specification in the upcoming 20-30nm node and
beyond.
Novel optical proximity correction (OPC) and design for manufacturability (DfM) methodology for threedimensional
(3D) memory device is proposed to overcome emerging hotspot issues caused by larger process proximity
effect (PPE) due to unavoidable high-aspect patterning process. To realize robust pattern formation for lithography and
reactive-ion etching (RIE) processes, the following methodologies are introduced: i) OPC is carried out by using
averaged or designed optics not ideal to make robust pattern formation for optical variation of exposure tool, ii)
lithography compliance check (LCC) is done under the worst optical condition to detect hotspots induced by optical
variation of exposure tool, and modification of layout and OPC condition is performed to remove hotspots, iii) hotspots
induced by RIE process are checked by using etching simulation with empirical RIE model, and modification of layout,
PPC and OPC scheme is performed to remove hotspots. In this study, it is confirmed that our proposed novel OPC and
DfM methodology is promising for robust pattern formation in upcoming 3D memory device.
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