Advanced DRAM technology relies heavily on 193nm immersion lithography. Negative tone develop (NTD) layers are becoming increasingly important particularly in nodes below 20nm. NTD is particularly useful for patterning holes on the wafer. Cut layers for multi-patterning (MP) applications and bit line contact structures are common uses of NTD in DRAM. Patterning these structures pose lithographic challenges around process window (PW), layer-to-layer overlay, and critical dimension (CD) control. The mask plays a critical role in optimizing all of these attributes. In this paper, we explore multiple mask enhancements to optimize wafer performance for NTD contacts. These include mask process and mask blank conditions, as well as a data enhancement technique generally known as mask process correction (MPC). Specifically, we implement a litho-aware MPC Application (LAMA) to optimize mask pattern fidelity. Finally, we harmonize these mask enhancements with optimizations to wafer exposure conditions and optical proximity correction (OPC) to demonstrate capability improvement in NTD contact lithography.
As feature sizes diminish and correction flow complexity increases, it becomes extremely difficult to create homogeneous mask synthesis correction recipes that can pass lithographic verification without some failing hotspots. When encountered in the production line, these areas are frequently fixed quickly so the tapeout can resume and time-tomask is preserved as much as possible. However, these hotspots may occur in future designs, so it is beneficial to update the standard correction recipe with this hotspot information and avoid verification failures before they occur. This paper examines inserting unique hotspot corrections into the standard correction flow using pattern matching to identify the hotspot areas. Standard correction recipes can be updated to accept these hotspot areas and adjust recipe parameters or correction techniques in a standard manner so that these hotspots will be fixed automatically. This automation technique minimizes human interaction with the recipe.
Currently advanced DRAM design is beyond ArFi resolution limit, especially for the challenging processes in memory cell and core circuit pattern . When devices keep shrinking, multi-patterning with ArFi becomes more and more difficult to reach the process requirements in terms of pattern decomposition, process window loss with complex process integration, defect, and immersion resolution limits. Besides multi-patterning also suffers design cost, mask learning cycle and layout restriction. Currently 0.33NA EUV can provide 16nm pattern single exposure and cover all design circuit requirement. High resolution enhances 2D pattern process window for friendly layout design and better OVL control so it is a good choice to introduce EUV process for DRAM manufacturing.
We evaluate to apply EUV in memory cell instead of the two possible solutions of SADP with cut layer and LELE trimming with multi-mask to simplify processes. Memory cell is periodic main feature for the most area on a mask and dominates the most EUV OPC run time in full shot correction. In this paper we try to find a best way to handle cell area OPC and evaluate single mask to accomplish memory cell patterning.
Model-based optical proximity correction (OPC) is an indispensable production tool enabling successful extension of
photolithography down to sub-80nm regime. Commercial OPC software has established clear procedures to produce
accurate OPC models at best focus condition. However, OPC models calibrated at best focus condition sometimes fail to
prevent catastrophic circuit failure due to patterning short & open caused by accidental shifts of dose/ focus within the
corners of allowed processes window.
A novel model-based OPC verification methodology is presented in this work, which precisely pinpoints post OPC
photolithography failures in VLSI circuits through the entire lithographic process window. By application of a critical
photolithography process window model in OPC verification software, we successfully uncovered all weak points of a
design prior tape out, eliminating high risk of circuits open & shorts at the extreme corner of the lithographic process
window in any complex circuit layout environment. The process window-related information is usually not taken into
consideration when running OPC verification procedures with models calibrated at nominal process condition.
Intensive review of the critical dimension (CD) and top-view SEM micrographs from the weak points indicate matching
between post OPC simulation and measurements. Using a single highly accurate process window resist model provides a
reliable OPC verification methodology when used in a field- or grid-based simulation engine ensuring manufacturability
within the largest possible process window for any modern critical design.
For state of the art technologies, rule based optical proximity correction (OPC) together with conventional illumination is commonly used for contact layers, because it is simple to handle and processing times are short. However, as geometries are getting smaller it becomes more difficult to accurately control critical dimension (CD) variations influenced by nearby pattern. This applies in particular for irregularly arranged contact holes. Here simulation based OPC is more effective. We present a procedure for application of simulation based OPC for a 193 nm lithography contact hole layer with rectangular contact holes of different sizes in different proximities, using attenuated phase shift masks. In order to further improve the accuracy of the simulation based OPC process, characteristics of the mask, like mask corner rounding are incorporated in the OPC process. We build an OPC model, use it for OPC processing of DRAM design data and investigate the process window of the printing contacts. The results show an overlapping process window for length and width of isolated and dense small contact holes of different length and width, which is sufficient for volume production.