One of the limiting factors that have prevented a widely dissemination of the reconfigurable technology is the absence of an appropriate model for certain target applications capable of offering a reliable control. Moreover, the lack of flexible and easy-to-use scheduling and management systems are also relevant drawbacks to be considered. Under static scenarios, it is relatively easy to schedule and manage the reconfiguration process since all the variations corresponding to predetermined and well-known tasks. However, the difficulty increases when the adaptation needs of the overall system change semi-randomly according to the environmental fluctuations. In this context, this work proposes a change in the paradigm of dynamically reconfigurable systems, by attending to the dynamically reconfigurable control problematic as a whole, in which the scheduling and the placement issues are packed together as a hierarchical management structure, interacting together as one entity from the system point of view, but performing their tasks with certain degree of independence each other. In this sense, the top hierarchical level corresponds with a dynamic scheduler in charge of planning and adjusting all the reconfigurable modules according to the variations of the external stimulus. The lower level interacts with the physical layer of the device by means of instantiating, relocating, removing a reconfigurable module following the scheduler’s instructions. In regards to how fast is the proposed solution, the total partial reconfiguration time achieved with this proposal has been measured and compared with other two approaches: 1) using traditional Xilinx’s tools; 2) using an optimized version of the Xilinx's drivers. The collected numbers demonstrate that our solution reaches a gain up to 10 times faster than the other approaches.
One of the most computational intensive tasks in recent video encoders and decoders is the deblocking filter. Its
computational complexity is considerable, and it might take more than 30% of the total computational cost of the
decoder execution. Nowadays, some of its limiting factors for reaching real-time capabilities are mainly related with
memory and speed. Trying to deal with these factors, this paper proposes a novel Deblocking filter architecture which
supports all filtering modes available in both the H.264/AVC and Scalable Video Coding (SVC) standards. It has been
implemented in a hardware scalable architecture, which benefits of the parallelism and adaptability of the algorithm and
which can be adapted dynamically in FPGAs.
Regarding to the parallelism, this architecture mapping is capable of respecting data dependencies among MBs while
several functional units (FU) are filtering data in parallel. Regarding scalability, the architecture is flexible enough for
adapting its performance to the diverse environment demands. This fact is possible by increasing or decreasing the
number of FUs, like in a systolic array. In this sense, this paper will present a composition between the FU proposed
against the state-of-the art work.
In a short period of time, the multimedia sector has quickly progressed trying to overcome the exigencies of the
customers in terms of transfer speeds, storage memory, image quality, and functionalities. In order to cope with this
stringent situation, different hardware devices have been developed as possible choices. Despite of the fact that not every
device is apt for implementing the high computational demands associated to multimedia applications; reconfigurable
architectures appear as ideal candidates to achieve these necessities. As a direct consequence, worldwide universities and
industries have incremented their research activity into this area, generating an important know-how base. In order to
sort all the information generated about this issue, this paper reviews the most recent reconfigurable architectures for
multimedia applications. As a result, this paper establishes the benefits and drawbacks of the different dynamically
reconfigurable architectures for multimedia applications according to their system-level design.