Luxtera and TSMC have jointly developed a new generation 100Gbps/λ-capable silicon photonics platform in a commercial 300 mm CMOS line. We present process details and the performance of the photonic device library.
In this paper we discuss design and characterization of silicon-photonics-based 100 Gbps (4×26 Gbps) transceivers for parallel single mode fiber communication. We also address some key underlying technologies including silicon photonics wafer processing, photonic device libraries, light source integration and packaging technologies.
Shared shuttle runs are an important factor of the microelectronics business ecosystem, allowing fabless semiconductor
companies to access advanced processes and supporting the development of new tools and processes. We report on the
creation and progress of a shared shuttle program for access to advanced silicon photonics optoelectronic platforms that
we expect will create a similar environment for the field of integrated photonics.
We report on the performance of an integrated four-channel parallel optical transceiver built in a CMOS photonics
process, operating at 28 Gb/s per channel. The optical engine of the transceiver comprises a single silicon die and a
hybrid integrated DFB laser. The silicon die contains the all functionalities needed for an optical transceiver: transmitter
and receiver optics, electrical driver, receiver and control circuits. We also describe the CMOS photonics platform used
to build such transceiver device, which consists of: an optically enabled CMOS process, a photonic device library, and a
design infrastructure that is modeled after standard circuit design tools. We discuss how this platform can scale to higher
speeds and channel counts.
Silicon photonics is envisioned as a promising solution to address the interconnect bottleneck
in large-scale multi-processor computing systems, owing to advantageous attributes such as wide
bandwidth, high density, and low latency. To leverage these advantages, optical proximity coupler is
one of the critical enablers. Chip-to-chip, layer-to-layer optical proximity couplers with low loss,
large bandwidth, small footprint and integration compatibility are highly desirable. In this paper, we
demonstrate chip-to-chip optical proximity coupling using grating couplers. We report the
experimental results using grating couplers fabricated in a photonically-enabled commercial 130nm
SOI CMOS process.
Ring waveguide resonating structures with high quality factors are the key components servicing silicon
photonic links. We demonstrate highly efficient spectral tunability of the microphotonic ring structures
manufactured in commercial 130 nm SOI CMOS technology. Our rings are fitted with dedicated heaters
and integrated with silicon micro-machined features. Optimized layout and structure of the devices result in
their maximized thermal impedance and increased efficiency of the thermal tuning.
We present a hybrid integration technology platform for the compact integration of best-in-breed VLSI and photonic
circuits. This hybridization solution requires fabrication of ultralow parasitic chip-to-chip interconnects on the candidate
chips and assembly of these by a highly accurate flip-chip bonding process. The former is achieved by microsolder bump
interconnects that can be fabricated by wafer-scale processes, and are shown to have average resistance <1 ohm/bump
and capacitance <25fF/bump. This suite of technologies was successfully used to hybrid integrate high speed VLSI chips
built on the 90nm bulk CMOS technology node with silicon photonic modulators and detectors built on a 130nm
CMOS-photonic platform and an SOI-photonic platform; these particular hybrids yielded Tx and Rx components with
energies as low as 320fJ/bit and 690fJ/bit, respectively. We also report on challenges and ongoing efforts to fabricate
microsolder bump interconnects on next-generation 40nm VLSI CMOS chips.
Scaling of high performance, many-core, computing systems calls for disruptive solutions to provide ultra energy
efficient and high bandwidth density interconnects at very low cost. Silicon photonics is viewed as a promising solution.
For silicon photonics to prevail and penetrate deeper into the computing system interconnection hierarchy, it requires
innovative optical devices, novel circuits, and advanced integration. We review our recent progress in key building
blocks toward sub pJ/bit optical link for inter/intra-chip applications, ultra-low power silicon photonic transceivers. In
particular, compact reverse biased silicon ring modulator was developed with high modulation bandwidth sufficient for
15Gbps modulation, very small junction capacitance of ~50fF, low voltage swing of 2V, high extinction ratio (>7dB)
and low optical loss (~2dB at on-state). Integrated with low power CMOS driver circuits using low parasitic microsolder
bump technique, we achieved record low power consumption of 320fJ/bit at 5Gbps data rate. Stable operation with biterror-
rate better than 10-13 was accomplished with simple thermal management. We further review the first hybrid
integrated silicon photonic receiver based on Ge waveguide photo detector using the same integration technique, with
which high energy efficiency of 690fJ/bit, and sensitivity of ~18.9dBm at 5Gbps data rate for bit-error-rate of 10-12 were
Ring waveguide resonating structures with high quality factors are the key components in the silicon photonics portfolio
boosting up its functionality and circuit performance. Due to a number of manufacturing reasons their peak wavelengths
are often prone to deviate from designed values. In order to keep the ring resonator operating as specified, its peak
wavelength then needs to be corrected in a reliable and power efficient way. We demonstrate the performance of the
thermally tunable mux/demux filter ring structures fabricated in the commercial 130 nm SOI CMOS line.
The Ultra-performance Nanophotonic Intrachip Communication (UNIC) project aims to achieve unprecedented high-density,
low-power, large-bandwidth, and low-latency optical interconnect for highly compact supercomputer systems.
This project, which has started in 2008, sets extremely aggressive goals on power consumptions and footprints for
optical devices and the integrated VLSI circuits. In this paper we will discuss our challenges and present some of our
first-year achievements, including a 320 fJ/bit hybrid-bonded optical transmitter and a 690 fJ/bit hybrid-bonded optical
receiver. The optical transmitter was made of a Si microring modulator flip-chip bonded to a 90nm CMOS driver with
digital clocking. With only 1.6mW power consumption measured from the power supply voltages and currents, the
transmitter exhibits a wide open eye with extinction ratio >7dB at 5Gb/s. The receiver was made of a Ge waveguide
detector flip-chip bonded to a 90nm CMOS digitally clocked receiver circuit. With 3.45mW power consumption, the
integrated receiver demonstrated -18.9dBm sensitivity at 5Gb/s for a BER of 10-12. In addition, we will discuss our
Mux/Demux strategy and present our devices with small footprints and low tuning energy.
In this paper we present a computing system that uniquely leverages the bandwidth, density, and
latency advantages of silicon photonic interconnects to enable highly compact supercomputerscale
systems. We present the details of an optically enabled "macrochip" which is a set of
contiguous, optically-interconnected chips that deploy wavelength-division multiplexed (WDM)
enabled by silicon photonics. We describe the system architecture and the WDM point-to-point
network implementation of a "macrochip" providing bisection bandwidth of 10 TBps and discuss
system and device level challenges, constraints, and the critical technologies needed to implement
this system. We present a roadmap to lowering the energy-per-bit of a silicon photonic
interconnect and highlight recent advances in silicon photonics under the UNIC program that
facilitate implementation of a "macrochip" system made of arrayed chips.
We report on the development of single-chip, monolithically-integrated 40 Gbps transceivers built in a 130 nm SOI
CMOS process as part of Phase II of the DARPA EPIC program. In this talk we give an overview of the system
architecture, including the transmit and receive paths as well as the control systems. We report on the performance of
the individual building blocks, and discuss a scaling to 100 Gbps and beyond single-chip transceivers built in CMOS
We present our approach to a low-cost, highly scalable opto-electronic integration platform based on a commercial
CMOS process. In this talk, we detail the performance of the device library elements and highlight performance trade-offs
encountered in monolithically integrating optical and electronic circuits. We describe an opto-electronic integrated
circuit (OEIC) design toolkit modeled after the standard electronic design flow, which includes automated design rule
checking (DRC) and layout-versus-schematic (LVS) checks covering all types of circuit elements. As an example of
integration, we detail the design of a multi-channel transceiver chip with 10 Gbps/channel optical data transmission
speed and report on its performance.
We demonstrate an optical parametric oscillator (OPO) based on GaAs. The OPO utilized an all-epitaxially-grown orientation-patterned GaAs (OP-GaAs) crystal, 0.5-mm-thick, 5-mm-wide, and 11-mm-long, with a domain reversal period of 61.2 microns. By tuning either the near-IR pump wavelength between 1.75 and 2 microns, or the temperature of the GaAs crystal, the mid-IR output tuned between 2 and 11 microns, limited only by the spectral range of the OPO mirrors. The pump threshold of the singly-resonant OPO was 16 micro-J for the 6-ns pump pulses, and the photon conversion slope efficiency reached 54%. Also, we show experimentally the possibility of pump-polarization-independent frequency conversion in GaAs.
We demonstrate an optical parametric oscillator (OPO) based on GaAs. The OPO utilized an all-epitaxially-grown orientation-patterned GaAs (OP-GaAs) crystal, 0.5-mm-thick, 5-mm-wide, and 11-mm-long, with a domain reversal period of 61.2 μm. By tuning either the near-IR pump wavelength between 1.75 and 2 μm, or the temperature of the GaAs crystal, the mid-IR output tuned between 2 and 11 μm, limited only by the spectral range of the OPO mirrors. The pump threshold of the singly-resonant OPO was 16 μJ for the 6-ns pump pulses, and the photon conversion slope efficiency reached 54%. Also, we show experimentally the possibility of pump-polarization-independent frequency conversion in GaAs.
Lightsources employing quasiphasematched (QPM) nonlinear materials have demonstrated unique attributes for chemical sensing in the near- to mid-infrare spectral range (1 - 5 micrometers ). The advent of patterned-growth GaAs allows the first practical extension of QPM materials to operation in the long-wave IR (5 - 12 micrometers ). That wavelength range is particularly attractive for chemical sensing because it contains an atmospheric window, many molecular groups absorb there at distinct frequencies, and their absorptions tend to be strong relative to those in the near- and mid-IR. Here, the application of orientation-patterned GaAs (OPGaAs) for use in a continuous wave (cw) difference frequency spectrometer is described. The outputs of two external- cavity diode lasers operating in the 1.3 and 1.5 micrometers telecom bands are mixed in a OPGaAs crystal, producing tunable radiation at wavelengths near 8 micrometers . The application of the source to the measurement of a water vapor rovibrational absorption line is presented.