This work investigates both DC and pulse electroplating techniques for nickel. A nickel sulfamate electrolyte is utilized for nickel deposition over Cu/Ti coated silicon substrates. Stress levels and grain morphology are investigated and analyzed for the electroplated nickel deposit. A comparison is also made between the results obtained from DC and from long and short duration pulse electroplating techniques. Both compressive and tensile built-in stresses are observed in both DC and long duration pulse plated nickel while only compressive stresses are observed in short duration pulse plated nickel.
A post-CMOS process for chip-level monolithic integration has been developed. A metal probe array for recording neural signals is utilized as a test vehicle to realize the integration process. This probe array is fabricated on a 2 mm x 2 mm chip containing eight ultra-low power CMOS operational amplifiers. A LIGA-like process is employed utilizing UV lithography on SU-8 photoresist and pulse electroplating technique. Pulse plating significantly reduces stress in the deposited material. The post-CMOS fabrication process is utilized to fabricate 70 μm high probes having different aspect-ratios that are monolithically integrated on the CMOS chip.
A microprobe array for recording neural signals has been designed and fabricated for future monolithic integration with an ultra-low power CMOS operational amplifier circuit on a 2 mm × 2 mm chip. A LIGA-like process is employed utilizing UV lithography and electrodeposition techniques. Probes are fabricated on silicon substrate. The fabrication process is compatible with monolithic integration with CMOS signal processing circuitry. The probes are 210 um high and have an aspect ratio 3:1. Comments are made on processing issues related to chip-level monolithic integration.
A CMOS test chip has been designed and fabricated which can monolithically integrate ultra low-power operational amplifiers with neural microprobes through post-IC processing. Neural microprobes of varying widths (70 μm, 60 μm, 50 μm, and 40 μm) are designed with varying center-to-center spacing (195 μm, 175 μm, 165 μm, 155 μm, 145 μm, and 125 μm) on a test chip for integration. Neural microprobes are first fabricated on a separate Si substrate to develop a fabrication process for post-IC processing for integration. The amplifier is designed in standard 1.5 μm CMOS process for operation at ∓ 0.4 V. Low power performance is realized by combining forward biased source-substrate junction MOSFETs with a novel low-voltage level-shift current mirror. The designed amplifier gives a gain of 7000 (77 dB) and a 3-dB bandwidth of 30 kHz. The amplifier output has a positive offset of only 20 μV and power dissipation of only 40 μW.
In our previous work, we had reported initial results on electrical behavior of a novel device called Laterally Movable Gate Field Effect Transistor or LMGFET. In this device, the gate of a FET moves parallel to the substrate surface, which causes the drain current to change linearly to gate motion. In this paper, we describe a potential application of this device as a resonant gate structure. A folded beam structure is utilized as a restraining spring in order to make spring more flexible in the direction of motion compared to the other two orthogonal directions. A high aspect ratio structure is utilized to decrease motion in the direction vertical to the substrate. The resonance frequency can be changed with device geometry resulting in an array of devices with different resonance frequencies on a chip. Five different resonant gate structures are designed with resonance frequencies lying in the audio frequency range. The structures are simulated by analytical and numerical methods. Damping effects are considered in the simulations resulting in quality factor Q values in the range of 500 to 1440 under atmospheric conditions for the designed structures.
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