A methodology is described wherein a calibrated model-based ‘Virtual’ Variable Shaped Beam (VSB) mask writer
process simulator is used to accurately verify complex Optical Proximity Correction (OPC) and Inverse Lithography
Technology (ILT) mask designs prior to Mask Data Preparation (MDP) and mask fabrication. This type of
verification addresses physical effects which occur in mask writing that may impact lithographic printing fidelity
and variability. The work described here is motivated by requirements for extreme accuracy and control of
variations for today’s most demanding IC products. These extreme demands necessitate careful and detailed
analysis of all potential sources of uncompensated error or variation and extreme control of these at each stage of
the integrated OPC/ MDP/ Mask/ silicon lithography flow. The important potential sources of variation we focus on
here originate on the basis of VSB mask writer physics and other errors inherent in the mask writing process. The
deposited electron beam dose distribution may be examined in a manner similar to optical lithography aerial image
analysis and image edge log-slope analysis. This approach enables one to catch, grade, and mitigate problems early
and thus reduce the likelihood for costly long-loop iterations between OPC, MDP, and wafer fabrication flows. It
moreover describes how to detect regions of a layout or mask where hotspots may occur or where the robustness to
intrinsic variations may be improved by modification to the OPC, choice of mask technology, or by judicious design
of VSB shots and dose assignment.
Current flash memory technology is facing more and more challenges for 45nm and 32nm node technology. To get good
CD and yield control, optimized RET, OPC modeling and DFM techniques have to be applied . To enhance process
window (PW) and better CD control for main features, assist features (SB) have to be used. Simulation and wafer
evaluation show that the SB CD performance is very critical. Based on OPC simulation, we can get a very good
prediction about the CD size and placement of assist features. However, we can not always get what we want from mask
suppliers. For 45nm node technology and beyond, The SB CD size (~ 20nm at 1X) has almost pushed to the current
mask process limit. Wafer fabs have a very big concern about the stability of linearity signatures from different
suppliers and different products in order to keep high accuracy of OPC models. Actually the CD linearity signature
varies from one mask supplier to another and also varies from product to product. To improve the SB CD control, the
ideal goal is to make "flat" linearity for all mask suppliers. By working closely with TPI mask supplier, we come up
solutions to improve SB CD control to get "flat" linearity. Also technology development is causing more severe SB
printability, we proposed a methodology to use AIMS for predicting SB printability. Wafer results proved the feasibility
for these methodologies.
In this paper advanced OPC (Optical Proximity Correction) methods, additional with assistant features, and non-obvious
methods were implemented to correct aberrations caused by aggressive illuminations in order to optimize the shape of
the finger tips. OPC model and simulations were verified using 2D verification method.
Acceptance of Sub Resolution Assist Feature (SRAF) has been widely recognized in lithography patterning. In general,
with the insertion of SRAF in optically adjacent space area of design main feature, the aerial image intensity profiles of
the corresponding main features are apparently being either constructively or destructively alternated at imaging plane
[Figure 1]. From lithography patterning perspective, the optimized or better pattern imaging process requires
constructive SRAF. Such SRAF is inserted into available space for main feature to obtain optimal or better image
contrast, better imaging resolution and depth of focus (DOF) which is similar or close to optimal focus latitude.
However, the complementary destructive SRAF insertion can adversely occur in certain circumstances. In this paper, we
study the theoretical understanding of the constructive and destructive effects against design main features imaging
associated with the efforts to include SRAF (it's either driven by rule, model or mishap). In addition, an evaluation
scheme is developed and being explored in many aspects in order to describe the constructive and destructive response of
inserted SRAF. Such evaluation scheme has derived an application to detect the degree of SRAF insertion coverage
accuracy, impact on manufacturing, and most usefully, to access potential layout required optimization in design space
based on these complementary effects mechanism throughout several off-axis illumination conditions.
Patterning of dense gratings with sub-wavelength pitches presents a challenge that can be addressed using Resolution Enhancement Techniques (RETs) such as dipole illumination, with the dipole axis perpendicular to the dense line orientation. However, this approach leads to pitch and orientation limitations that must be accommodated in layout practices and design rules. In this work we evaluate the impact that dipole illumination has on the process window of isolated lines and loose pitch lines parallel and orthogonal to the dipole axis, and demonstrate the use of OPC and design restrictions to minimize this impact. Semi-dense and isolated features need to be treated as a function of their orientation with respect to the dipole. Specifically, isolated features oriented along the axis of the dipole have larger process margins than the same feature oriented perpendicular to this axis. We systematically explore the process margins for various CDs, pitches and orientations, and compare the results with simulations. We demonstrate that the dipole illumination restricts the ranges of sizes, pitches and orientations that can be printed with sufficient process margin. Knowledge of these restrictions and comparing them with simulation enables us to evaluate the suitability of simulations as a predictor for design rules to restrict layout. The results enable us to propose design rules that would enable single-mask solutions for layers using dipole illumination.
As geometries continue to shrink and the equipment is pushed closer to its true limits, overlay and other printing parameters become a larger part of the total budget. Overlay and CD measurements are sampled 'in line' to track and target tools. Adding these parameters to the electrically tested database along with sort data improves yield correlation and failure analysis both during development and in manufacturing. Typically electrical alignment structures such as a resistor divider work well for a few layers but are limited to layers connecting to resistor elements. This paper describes a novel resistor ladder structure that can measure alignment between any 2 conducting layers as well as measure tip pullback, layer to layer patterning impacts, and other characteristics in real device type layouts. Only mask generation and wafer printing capabilities limit the accuracy of the measurement.