The accuracy and efficiency of OPC (Optical Proximity Correction) modeling have become paramount important at the
low k1 lithography. However the accuracy of OPC model has to compromise with the efficiency of model calibration
and pattern correction, since the model accuracy is usually improved by using more kernels to represent the model but
the runtime of model setup and pattern correction also increase as kernel count increasing.
A novel decomposition of source kernel for OPC model calibration was presented in this study to maintain the model
accuracy and preserve the OPC runtime at acceptable level. Firstly, the source kernel was decomposed into multiple subsource
kernels and then the magnitude of electric field for each decomposed sub-source was modulated in frequency
domain. Finally, the resultant source can be the combination of many different sub-sources to represent the tool-specific
characteristics. The model accuracy, model stability and modeling runtime were compared among decomposed source,
ideal source and measured source models. The results showed modeling residual RMS error, predictive capability of
decomposed source can be reduced to be comparable to measured source and superior to the ideal source. As for the
modeling efficiency, the decomposed source is up to 5 times faster than the measured source but just few percentages
slower than the ideal source approach.
Attenuated PSM (Phase Shift Mask) has been widely adopted in contact lithography to enhance the resolution and process latitude. While the main drawback associated with the use of attenuated PSM is the side lobe printing, which yields unwanted resist erosion of area among patterned holes. Side lobes, if etched and filled in the following semiconductor processing, can cause electrical shorting, chip failure and device reliability problem, hence any side lobes are extremely undesirable. Usually, the side lobe detection for simple layouts can be conducted manually through the help of lithography simulation tools, but the detection of potential side lobe printing becomes far more challenging for full-chip production layouts. An efficient side-lobe detection approach was demonstrated in this study, with the use of assistant ring, polygon-based simulation instead of grid-based simulation has been enabled for full-chip side lobe detection. Furthermore, a model-based method for side lobe suppression was also demonstrated in our flow.
As the semiconductor feature size continues to shrink, the high NA lithography has become a reality. Coupling with high NA lithography, both the critical dimension control and the insufficient resist thickness for etch mask are becoming major challenges for lithographers. Hence two things are highly desired, one is an effective anti-reflective coating (ARC) strategy to maintain low reflectance for good critical dimension (CD) uniformity (CDU) control, and the other is combined ARC and hard-mask concept to satisfy both lithography and etch performance needs for feature patterning. In this study, a dual dielectric anti-reflective coating (dual-DARC) was first demonstrated as an effective ARC for contact application with high NA lithography. The ordinary single DARC is very sensitive to the thickness variation of underlying films, resulting in a >45nm contact CD variation at interlayer dielectric (ILD) thickness variation of ±150nm induced by CMP process. Unlike the single DARC, the dual-DARC performs a less CD variation of ~5nm at the same film thickness variation. By extending the dual-DARC concept to combined ARC/hard-mask application to contact and poly patterning, several ARC/hard-mask schemes were compared by reflectance control, CD uniformity control and etch hard-mask performance. Apart from the good reflectance and CD uniformity control of dual-DARC-like schemes, the most attractive is that the proper use of dual-DARC concept to hard-mask application, the tight thickness control is not necessary for the bottom layer and you can just tailor the bottom layer's thickness to meet the individual process needs.
As semiconductor technologies move toward 0.18um and below, it is difficult to get high pattern fidelity by 248-nm wavelength exposure. To reduce proximity effect, a lot of resolution enhancement technologies (RET) such as OPC, assistant feature, and double exposure technologies (DET) have been introduced. In this paper, random contact holes with low proximity effect were delivered by using 248-nm exposure tool in conjunction with double exposure technology. A low proximity resist patterns were formed by a well-designed Pack-mask. Then ion implantation treatment produced a solvent proof skin on the developed resist. The second lithography process was performed over the post-implanted resist layer. Resist coating as well as exposure perfectly transfer the patterns from Cover-mask. After etch, random holes with low proximity effect were easily achieved. In addition, higher energy association with higher dosages is able to maintain good critical dimension even if wafers went through three rework processes.