High defect density in thermodynamics driven DSA flows has been a major cause of concern for a while and several questions have been raised about the relevance of DSA in high volume manufacturing. The major questions raised in this regard are: 1. What is the intrinsic level of DSA-induced defects, 2. Can we isolate the DSA-induced defects from the other processes-induced defects, 3. How much do the DSA materials contribute to the final defectivity and can this be controlled, 4. How can we understand the root causes of the DSA-induced defects, their kinetics of annihilation and finally, 5. Can we have block co-polymer anneal durations that are compatible with standard CMOS fabrication techniques (in the range of minutes) with low defect levels. This manuscript addresses these important questions and identifies the issues and the level of control needed to achieve a stable DSA defect performance.
Directed self-assembly (DSA) is being actively investigated as a potential patterning solution for future generation devices. While SEM based CD measurement is currently used in research and development, scatterometry-based techniques like spectroscopic CD (SCD) are preferred for high volume manufacturing. SCD can offer information about sub-surface features that are not available from CD-SEM measurement. Besides, SCD is a non-destructive, high throughput technique already adopted in HVM in several advanced nodes. The directed self assembly CD measurement can be challenging because of small dimensions and extremely thin layers in the DSA stack. In this study, the SCD technology was investigated for a 14 nm resolution PS-b-PMMA chemical epitaxy UW process optimized by imec. The DSA stack involves new materials such as cross-linkable polysterene (XPS) of thickness approximately 5 nm, ArF immersion resist (subsequently removed), -OH terminated neutral brush layer, and BCP material (Polystyrene-blockmethyl methacrylate of thickness roughly 20 to 30 nm). The mask contains a large CD and pitch matrix, for studying the quality of self-assembly as a function of the guide pattern dimensions. We report on the ability of SCD to characterize the dimensional variation in these targets and hence provide a viable process control solution.
Next-generation lithography technology is required to meet the needs of advanced design nodes. Directed Self Assembly (DSA) is gaining momentum as an alternative or complementary technology to EUV lithography. We investigate defectivity on a 2xnm patterning of contacts for 25nm or less contact hole assembly by grapho epitaxy DSA technology with guide patterns printed using immersion ArF negative tone development. This paper discusses the development of an analysis methodology for DSA with optical wafer inspection, based on defect source identification, sampling and filtering methods supporting process development efficiency of DSA processes and tools.
Directed Self-Assembly (DSA) of Block Co-Polymers (BCP) has become an intense field of study as a potential patterning solution for future generation devices. The most critical challenges that need to be understood and controlled include pattern placement accuracy, achieving low defectivity in DSA patterns and how to make chip designs DSA-friendly. The DSA program at imec includes efforts on these three major topics. Specifically, in this paper the progress in DSA defectivity within the imec program will be discussed. In previous work, defectivity levels of ~560 defects/cm2 were reported and the root causes for these defects were identified, which included particle sources, material interactions and pre-pattern imperfections. The specific efforts that have been undertaken to reduce defectivity in the line/space chemoepitaxy DSA flow that is used for the imec defectivity studies are discussed. Specifically, control of neutral layer material and improved filtration during the block co-polymer manufacturing have enabled a significant reduction in the defect performance. In parallel, efforts have been ongoing to enhance the defect inspection capabilities and allow a high capture rate of the small defects. It is demonstrated that transfer of the polystyrene patterns into the underlying substrate is critical for detecting the DSA-relevant defect modes including microbridges and small dislocations. Such pattern transfer enhances the inspection sensitivity by ~10x. Further improvement through process optimization allows for substantial defectivity reduction.
Directed Self-Assembly (DSA) is considered as a potential patterning solution for future generation devices. One of the
most critical challenges for translating DSA into high volume manufacturing is to achieve low defect density in the DSA
patterning process. The defect inspection capability is fundamental to defect reduction in any process, particularly the
DSA process, as it provides engineers with information on the numbers and types of defects. While the challenges of
other candidates of new generation lithography are well known (for example, smaller size, noise level due to LER etc.),
the DSA process causes certain defects that are unique. These defects are nearly planar and in a material which produces
very little defect scattering signal. These defects, termed as “dislocation” and “disclination” have unique shapes and have
very little material contrast. While large clusters of these unique defects are easy to detect, single dislocation and
disclination defects offer considerable challenge during inspection. In this investigation, etching the DSA pattern into a
silicon (Si) substrate structure to enhance defect signal and Signal-to-Noise Ratio (SNR) is studied. We used a Rigorous
Coupled-Wave Analysis (RCWA) method for solving Maxwell’s equations to simulate the DSA unique defects and
calculate inspection parameters. Controllable inspection parameters include various illumination and collection
apertures, wavelength band, polarization, noise filtering, focus, pixel size, and signal processing. From the RCWA
simulation, we compared SNR between “Post-SiN etch” and “Post-SiN+Si-substrate etch” steps. The study is also
extended to investigate wafer-level data at post etch inspection. Both the simulations and inspection tool results showed
dramatic signal and SNR improvements when the pattern was etched into the SiN+Si substrate allowing capture of DSA
unique defect types.
As design rule shrinks, it is essential that the capability to detect smaller and smaller defects should improve. There is considerable effort going on in the industry to enhance immersion lithography using directed self-assembly (DSA) for the 14-nm design node and below. While the process feasibility is demonstrated with DSA, material issues as well as process control requirements are not fully characterized. The chemical epitaxy process is currently the most-preferred process option for frequency multiplication, and it involves new materials at extremely small thicknesses. The image contrast of the lamellar line/space pattern at such small layer thicknesses is a new challenge for optical inspection tools. The study focuses on capability of optical inspection systems to capture DSA unique defects such as dislocations and disclination clusters over the system and wafer noise. The study is also extended to investigate wafer-level data at multiple process steps and to determine the contribution from each process step and materials using defect source analysis methodology. The added defect pareto and spatial distributions of added defects at each process step are discussed.
This paper discusses the defect density detection and analysis methodology using advanced optical wafer inspection capability to enable accelerated development of a DSA process/process tools and the required inspection capability to monitor such a process. The defectivity inspection methodologies are optimized for grapho epitaxy directed self-assembly (DSA) contact holes with 25 nm sizes. A defect test reticle with programmed defects on guide patterns is designed for improved optimization of defectivity monitoring. Using this reticle, resist guide holes with a variety of sizes and shapes are patterned using an ArF immersion scanner. The negative tone development (NTD) type thermally stable resist guide is used for DSA of a polystyrene-b-poly(methyl methacrylate) (PS-b-PMMA) block copolymer (BCP). Using a variety of defects intentionally made by changing guide pattern sizes, the detection rates of each specific defectivity type has been analyzed. It is found in this work that to maximize sensitivity, a two pass scan with bright field (BF) and dark field (DF) modes provides the best overall defect type coverage and sensitivity. The performance of the two pass scan with BF and DF modes is also revealed by defect analysis for baseline defectivity on a wafer processed with nominal process conditions.
As design rule shrinks, it is essential that the capability to detect smaller and smaller defects should improve. There is
considerable effort going on in the industry to enhance Immersion Lithography using DSA for 14 nm design node and
below. While the process feasibility is demonstrated with DSA, material issues as well as process control requirements
are not fully characterized. The chemical epitaxy process is currently the most-preferred process option for frequency
multiplication and it involves new materials at extremely small thickness. The image contrast of the lamellar Line/Space
pattern at such small layer thickness is a new challenge for optical inspection tools. In this investigation, the focus is on the capability for optical inspection systems to capture DSA unique defects such as dislocations and disclination clusters over the system and wafer noise. The study is also extended to investigate wafer level data at multiple process steps and determining contribution from each process step and materials using ‘Defect Source Analysis’ methodology. The added defect pareto and spatial distributions of added defects at each process step are discussed.
Reticle Pattern Placement Error (PPE) has been identified as one of the key challenges of Double-Patterning Lithography (DPL) as the overlay of the circuit patterns between two masks is a critical
achievement for successful implementation of the process. According to the 2009 ITRS roadmap, double-patterning
lithography is expected to extend 193nm immersion lithography to the 23nm node by 2016 and
the corresponding PPE requirements is 1.9nm. PPE between the two masks comprising a DPL mask pair
affects the resulting critical dimensions of the circuit pattern and the final device performance.
In this paper, we study how the reticle PPE can be affected by the pellicle. The pellicle can induce a
mechanical stress on the reticle such that the actual placement of the circuit patterns on wafer will be
distorted after the lithography process. This distortion effect is known as Pellicle-Induced Distortion (PID).
We conducted experiments by using different combinations of pellicle frames and frame adhesives on a
DPL mask pair to study how reticle PPE can change with each combination. We used the KLA-Tencor
LMS IPRO4 mask registration metrology tool to measure the PPE before and after the mount/un-mount of
each experiment combination. The analysis is done using the KLA-Tencor DEVA software to quantify how
the pellicle can affect the individual reticle PPE and also the relative errors between the DPL mask pair.
Improved overlay performance is one of the critical elements in enabling the continuing advancement of the
semiconductor integrated circuit (IC) industry. With each advancing process node, additional sources of overlay error
and new methods of reducing those errors need to be taken into account. We consider the impact of mask registration or
pattern placement errors on intra-field on-wafer overlay performance. Mask registration data is typically minimally
sampled and not well incorporated into the wafer fab overlay systems. In this work we consider mask-to-mask overlay
and point out the importance of high density sampling as well as the potential for improved mask qualification and
A primary concern when selecting an overlay sampling plan is the balance between accuracy and throughput. Two
significant inflections in the semiconductor industry require even more careful sampling consideration: the transition
from linear to high order overlay control, and the transition to dual patterning lithography (DPL) processes. To address
the sampling challenges, an analysis tool in KT-Analyzer has been developed to enable quantitative evaluation of
sampling schemes for both stage-grid and within-field analysis. Our previous studies indicated (1) the need for fully
automated solutions that takes individual interpretation from the optimization process, and (2) the need for improved
algorithms for this automation; both of which are described here.
Defect monitoring has become an integral part of semiconductor manufacturing process equivalent to metrology operations such as Critical Dimension measurement and Overlay. The process control on defectivity data has not received the same acceptance as other metrology parameters since the measured defect density can not be easily attributed to a specific equipment. In this work, the problems associated with SPC of defectivity data will be discussed in detail. A parameter known as Specific Defect Density has been defined which can be applied in an automatic mode to shut down an equipment which generates yield limiting defects.