Dr. Vincent J.I. Wiaux Profile

Dr. Vincent J.I. Wiaux

Researcher at imec

SPIE Involvement:

Author

Publications (56)

Proceedings Article | 10 April 2024 Presentation + Paper

OPC and modeling solution towards 0.55NA EUV stitching

Dongbo Xu, Werner Gillijns, Stewart Wu, Abdulrazaq Adams, Vincent Wiaux, Vicky Philipsen, Xima Zhang, Edita Tejnil, Germain Fenger

Proceedings Volume 12953, 129530K (2024) https://doi.org/10.1117/12.3010519

KEYWORDS: Optical proximity correction, Semiconducting wafers, Extreme ultraviolet lithography, Modeling, Scanners, Reticles

Read Abstract +

Proceedings Article | 10 April 2024 Presentation + Paper

High-NA benefit assessment through Zeiss AIMS EUV for tip-to-tip patterning by EUVL

Rik Jonckheere, Tatiana Kovalevich, Vincent Wiaux, Vicky Philipsen, Eric Hendrickx, Andreas Verch, Maximillian Albert, Renzo Capelli

Proceedings Volume 12953, 1295304 (2024) https://doi.org/10.1117/12.3011615

KEYWORDS: Extreme ultraviolet, Extreme ultraviolet lithography, Tantalum, Optical lithography, Scanners, Semiconducting wafers, Design, Logic

Read Abstract +

Proceedings Article | 10 April 2024 Presentation

Computational lithography and patterning evaluation to support EUV high-NA stitching

Cyrus Tabery, Jiuning Hu, Rongkuo Zhao, Christoph Hennerkes, Stephen Hsu, Yunbo Liu, Natalia Davydova, Victor Blanco, Vincent Wiaux

Proceedings Volume PC12953, PC129530M (2024) https://doi.org/10.1117/12.3012722

KEYWORDS: Optical lithography, Reticles, Extreme ultraviolet, Process control, Critical dimension metrology, Computational lithography, Design and modelling, Optical proximity correction, Imaging systems, Tantalum

Read Abstract +

Proceedings Article | 10 April 2024 Presentation + Paper

An experimental stitching study on the eve of high-NA EUV

Vincent Wiaux, Natalia Davydova, Lieve Van Look, Nick Pellens, Ataklti Weldeslassie, Guillaume Libeert, Tatiana Kovalevich, Frank Timmermans, Laura Huddleston

Proceedings Volume 12953, 129530J (2024) https://doi.org/10.1117/12.3010895

KEYWORDS: Critical dimension metrology, Reflectivity, Optical proximity correction, Light sources and illumination, Extreme ultraviolet, Design, Simulations, Scanners, Image processing, Modulation

Read Abstract +

Proceedings Article | 21 November 2023 Presentation + Paper

Stitching for high-NA: zooming in on CDU budget

Natalia Davydova, Lieve van Look, Ataklti Weldeslassie, Vincent Wiaux, Laura Huddleston, Bram Slachter, Nick Pellens, Frank Timmermans, Friso Wittebrood, Eelco van Setten, Daniel Wilson

Proceedings Volume 12750, 1275002 (2023) https://doi.org/10.1117/12.2687703

KEYWORDS: Critical dimension metrology, Zoom lenses, Reticles, Metrology, Image quality, Extreme ultraviolet, Stochastic processes, Statistical analysis, Semiconducting wafers, Overlay metrology

Read Abstract +

Proceedings Article | 21 November 2023 Presentation + Paper

A study of high NA EUV pattern stitching using rigorous stochastic lithography simulation

Stewart Robertson, Robert Schramm, Alessandro Vaglio Pret, Vincent Wiaux

Proceedings Volume 12750, 1275003 (2023) https://doi.org/10.1117/12.2688230

KEYWORDS: Stochastic processes, Reticles, Extreme ultraviolet, Extreme ultraviolet lithography, Semiconducting wafers, Scanners, Photoresist processing, Nanolithography, Modeling, EUV optics

Read Abstract +

Proceedings Article | 28 April 2023 Presentation + Paper

Overview of stitching for high NA: imaging and overlay experimental and simulation results

Natalia Davydova, Lieve van Look, Vincent Wiaux, Joost Bekaert, Frank Timmermans, Eelco van Setten, Bram Slachter, Laura Huddleston, Claire van Lare, Rongkuo Zhao, Dezheng Sun, Ming-Chun Tien, Marcel Beckers, Simon van Gorp, Cees Lambregts, Chung-Tien Li, Arthur van de Nes, Koen D'Havé, Tatiana Kovalevich, Diederik de Bruin, Stephen Hsu, Rene Carpaij

Proceedings Volume 12494, 124940Q (2023) https://doi.org/10.1117/12.2658511

KEYWORDS: Photomasks, Optical proximity correction, Reflection, Critical dimension metrology, Tantalum, Reflectivity, Metrology, Semiconducting wafers, Scanners, Reticles

Read Abstract +

Proceedings Article | 31 October 2022 Poster

Stitching for High NA: new insights and path forward

Natalia Davydova, Vincent Wiaux, Joost Bekaert, Frank Timmermans, Bram Slachter, Tatiana Kovalevich, Eelco van Setten, Marcel Beckers, Simon van Gorp, Rongkuo Zhao, Dezheng Sun, Ming-Chun Tien, Hoon Ser, Diederik de Bruin, Stephen Hsu, Rene Carpaij

Proceedings Volume PC12292, PC1229210 (2022) https://doi.org/10.1117/12.2653388

KEYWORDS: Tantalum, Image resolution, Source mask optimization, Scanners, Reflectivity, Optical proximity correction, Manufacturing, Extreme ultraviolet lithography, Control systems

Proceedings Article | 13 June 2022 Presentation

Resist and reticle activities towards High-NA EUV ecosystem readiness

Jara Santaclara, Weimin Gao, Eric Hendrickx, Vincent Wiaux, Joern-Holger Franke, Emily Gallagher, Kannan Keizer, Tatiana Kovalevich, Jo Finders

Proceedings Volume PC12051, PC1205105 (2022) https://doi.org/10.1117/12.2614162

KEYWORDS: Photomasks, Ecosystems, Optical lithography, Extreme ultraviolet, Reticles, Scanners, Metrology, Extreme ultraviolet lithography, Etching, Thin films

Read Abstract +

Proceedings Article | 4 January 2021 Presentation + Paper

Tomorrow’s pitches on today’s 0.33 NA scanner: pupil and imaging conditions to print P24 L/S and P28 contact holes

Joern-Holger Franke, Natalia Davydova, Joost Bekaert, Vincent Wiaux, Vineet Vijayakrishnan Nair, Andre van Dijk, Erik Wang, Mark Maslow, Eric Hendrickx

Proceedings Volume 11517, 1151716 (2021) https://doi.org/10.1117/12.2573073

KEYWORDS: Scanners, Extreme ultraviolet lithography, Etching, Metrology, Photomasks, Image quality, Semiconducting wafers, Semiconductors, Optical lithography, Ecosystems

Read Abstract +

Proceedings Article | 30 October 2020 Presentation + Paper

Stitching enablement for anamorphic imaging: a ~1μm exclusion band and its implications

Vincent Wiaux, Joost Bekaert, Tatiana Kovalevich, Julien Ryckaert, Eric Hendrickx, Natalia Davydova, Pieter Woltgens, Ming-Chun Tien, Laurens de Winter, Mark Maslow, Kars Troost

Proceedings Volume 11517, 1151713 (2020) https://doi.org/10.1117/12.2573155

KEYWORDS: Reticles, Semiconducting wafers, Photomasks, Imaging systems, Extreme ultraviolet, Optical proximity correction, Image resolution

Read Abstract +

Proceedings Article | 16 October 2020 Presentation + Paper

Experimental verification of high-NA imaging simulations using SHARP

Natalia Davydova, Fei Liu, Markus Benk, Eelco van Setten, Gerardo Bottiglieri, Anton van Oosten, John McNamara, Vincent Wiaux, Joern-Holger Franke, Kenneth Goldberg, DS Nam, Joseph Zekry, Patrick Naulleau, Timon Fliervoet, Rene Carpaij

Proceedings Volume 11517, 1151714 (2020) https://doi.org/10.1117/12.2572846

KEYWORDS: Scanners, Photomasks, Extreme ultraviolet lithography, Optical lithography, Reticles, Extreme ultraviolet, Microscopes, Light sources, Fiber optic illuminators, Projection systems

Read Abstract +

Proceedings Article | 12 October 2018 Presentation

Mask 3D effects experimental measurements with NA 0.55 anamorphic imaging (Conference Presentation)

Vincent Wiaux, Vicky Philipsen, Eric Hendrickx

Proceedings Volume 10809, 1080913 (2018) https://doi.org/10.1117/12.2501872

KEYWORDS: 3D metrology, Photomasks, 3D image processing, Stereoscopy, Solids, Extreme ultraviolet, Extreme ultraviolet lithography, Microscopes, Reticles

Read Abstract +

Proceedings Article | 19 March 2018 Presentation + Paper

Model based high NA anamorphic EUV RET

Fan Jiang, Vincent Wiaux, Germain Fenger, Chris Clifford, Vlad Liubich, Eric Hendrickx

Proceedings Volume 10583, 105830P (2018) https://doi.org/10.1117/12.2299668

KEYWORDS: Optical proximity correction, Photomasks, SRAF, Extreme ultraviolet, Image quality, Extreme ultraviolet lithography, Semiconducting wafers, Resolution enhancement technologies

Read Abstract +

With the announcement of the extension of the Extreme Ultraviolet (EUV) roadmap to a high NA lithography tool that utilizes anamorphic optics design, an investigation of design tradeoffs unique to the imaging of anamorphic lithography tool is shown. An anamorphic optical proximity correction (OPC) solution has been developed that models fully the EUV near field electromagnetic effects and the anamorphic imaging using the Domain Decomposition Method (DDM). Clips of imec representative for the N3 logic node were used to demonstrate the OPC solutions on critical layers that will benefit from the increased contrast at high NA using anamorphic imaging. However, unlike isomorphic case, from wafer perspective, OPC needs to treat x and y differently. In the paper, we show a design trade-off seen unique to Anamorphic EUV, namely that using a mask rule of 48nm (mask scale), approaching current state of the art, limitations are observed in the available correction that can be applied to the mask. The metal pattern has a pitch of 24nm and CD of 12nm. During OPC, the correction of the metal lines oriented vertically are being limited by the mask rule of 12nm 1X. The horizontally oriented lines do not suffer from this mask rule limitation as the correction is allowed to go to 6nm 1X. For this example, the masks rules will need to be more aggressive to allow complete correction, or design rules and wafer processes (wafer rotation) would need to be created that utilize the orientation that can image more aggressive features. When considering VIA or block level correction, aggressive polygon corner to corner designs can be handled with various solutions, including applying a 45 degree chop. Multiple solutions are discussed with the metrics of edge placement error (EPE) and Process Variation Bands (PVBands), together with all the mask constrains. Noted in anamorphic OPC, the 45 degree chop is maintained at the mask level to meet mask manufacturing constraints, but results in skewed angle edge in wafer level correction. In this paper, we used both contact (Via/block) patterns and metal patterns for OPC practice. By comparing the EPE of horizontal and vertical patterns with a fixed mask rule check (MRC), and the PVBand, we focus on the challenges and the solutions of OPC with anamorphic High-NA lens.

Proceedings Article | 19 March 2018 Presentation + Paper

Double patterning at NA 0.33 versus high-NA single exposure in EUV lithography: an imaging comparison

Weimin Gao, Vincent Wiaux, Wolfgang Hoppe, Vicky Philipsen, Lawrence Melvin, Eric Hendrickx, Kevin Lucas, Ryoung-han Kim

Proceedings Volume 10583, 105830O (2018) https://doi.org/10.1117/12.2297677

KEYWORDS: Photomasks, Optical proximity correction, Double patterning technology, Lithography, Extreme ultraviolet lithography, Image processing

Read Abstract +

Proceedings Article | 24 March 2017 Presentation + Paper

Modeling EUVL patterning variability for metal layers in 5nm technology node and its effect on electrical resistance

Weimin Gao, Victor Blanco, Vicky Philipsen, Itaru Kamohara, Yves Saad, Ivan Ciofi, Lawrence Melvin, Eric Hendrickx, Vincent Wiaux, Ryoung Han Kim

Proceedings Volume 10143, 101430I (2017) https://doi.org/10.1117/12.2259964

KEYWORDS: Extreme ultraviolet lithography, Optical lithography, 3D modeling, Data modeling, Resistance, Photomasks, Calibration, Stochastic processes, Semiconducting wafers

Read Abstract +

Proceedings Article | 1 October 2013 Paper

Imaging challenges in 20nm and 14nm logic nodes: hot spots performance in Metal1 layer

V. Timoshkov, D. Rio, H. Liu, W. Gillijns, J. Wang, P. Wong, D. Van Den Heuvel, V. Wiaux, P. Nikolsky, J. Finders

Proceedings Volume 8886, 88860N (2013) https://doi.org/10.1117/12.2030968

KEYWORDS: Reticles, Critical dimension metrology, Semiconducting wafers, Logic, Tolerancing, Double patterning technology, Standards development, Metals, Scanners

Read Abstract +

SPIE Journal Paper | 4 September 2013

Key contributors for improvement of line width roughness, line edge roughness, and critical dimension uniformity: 15 nm half-pitch patterning with extreme ultraviolet and self-aligned double patterning

Kaidong Xu, Laurent Souriau, David Hellin, Janko Versluijs, Patrick Wong, Diziana Vangoidsenhoven, Nadia Vandenbroeck, Harold Dekkers, Xiaoping Shi, Johan Albert, Chi Lim Tan, Johan Vertommen, Bart Coenegrachts, Isabelle Orain, Yoshie Kimura, Vincent Wiaux, Werner Boullart

JM3, Vol. 12, Issue 04, 041302, (September 2013) https://doi.org/10.1117/12.10.1117/1.JMM.12.4.041302

KEYWORDS: Line width roughness, Optical lithography, Etching, Line edge roughness, Photomasks, Silicon, Extreme ultraviolet lithography, Plasma, Plasma enhanced chemical vapor deposition, Lithography

Read Abstract +

Proceedings Article | 12 April 2013 Paper

Simulation of spacer-based SADP (Self-Aligned Double-Patterning) for 15nm half pitch

Stewart Robertson, Patrick Wong, Janko Versluijs, Vincent Wiaux

Proceedings Volume 8683, 86830Y (2013) https://doi.org/10.1117/12.2013877

KEYWORDS: Lithography, Etching, Double patterning technology, Optical lithography, Extreme ultraviolet lithography, Extreme ultraviolet, Semiconducting wafers, Ions, Design for manufacturability, Manufacturing

Read Abstract +

Proceedings Article | 29 March 2013 Paper

15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU

K. Xu, L. Souriau, D. Hellin, J. Versluijs, P. Wong, D. Vangoidsenhoven, N. Vandenbroeck, H. Dekkers, X. Shi, J. Albert, C. Tan, J. Vertommen, B. Coenegrachts, I. Orain, Y. Kimura, V. Wiaux, W. Boullart

Proceedings Volume 8685, 86850C (2013) https://doi.org/10.1117/12.2011586

KEYWORDS: Line width roughness, Etching, Optical lithography, Line edge roughness, Photomasks, Extreme ultraviolet lithography, Photoresist materials, Plasma, Silicon, Lithography

Read Abstract +

Proceedings Article | 13 March 2012 Paper

Litho1-litho2 proximity differences for LELE and LPLE double patterning processes

Patrick Wong, Peter De Bisschop, Stewart Robertson, Nadia Vandenbroeck, John Biafore, Vincent Wiaux, Jeroen Van de Kerkhove

Proceedings Volume 8326, 83260E (2012) https://doi.org/10.1117/12.916156

KEYWORDS: Double patterning technology, Semiconducting wafers, Data modeling, Finite element methods, Thermal modeling, Lithography, Metals, Photoresist processing, Surface plasmons, Optical lithography

Read Abstract +

Proceedings Article | 13 March 2012 Paper

Process development using negative tone development for the dark field critical layers in a 28nm node process

Janko Versluijs, Vincent Truffert, Gayle Murdoch, Peter De Bisschop, Darko Trivkovic, Vincent Wiaux, Eddy Kunnen, Laurent Souriau, Steven Demuynck, Monique Ercken

Proceedings Volume 8326, 83260W (2012) https://doi.org/10.1117/12.916700

KEYWORDS: Source mask optimization, Optical lithography, Etching, Semiconducting wafers, Photomasks, Immersion lithography, Metals, Lithography, Lithographic illumination, Image processing

Read Abstract +

The demand for ever shrinking semiconductor devices is driving efforts to reduce pattern dimensions in semiconductor lithography. In this work, the aim is to find a single patterning litho solution for a 28nm technology node using 193nm immersion lithography. Target poly pitch is 110nm and metal1 pitch is 90nm. For this, we have introduced a range of different techniques to reach this goal. At this node, it becomes essential to include the layout itself into the optimization process. This leads to the introduction of restricted design rules, together with the co-optimization of source and mask (SMO) and the use of customized illumination modes (freeform illumination sources; Flexray^TM). Also, negative tone development (NTD) is employed to further extend the applicability of 193nm immersion lithography. Traditionally, the printing of contacts and trenches is done by using a dark field mask in combination with a positive tone resist and positive tone development. The use of negative tone development enables images reversal. This allows benefiting from the improved imaging performance when exposing with bright field masks. The same features can be printed in positive tone resists and with improved process latitudes. At the same time intermediate metal (IM) layers are used to connect the front-end and back-end-of-line, resulting in huge area benefits compared to layouts without these IM layers. The use of these IM layers will not happen for the 28nm node, but is intended to be introduced towards the 20nm node, and beyond. Nevertheless, the choice was made to use this architecture to obtain a first learning cycle on this approach. In this study, the use of negative tone development is explored, and its use for the various dark field critical layers in a 28nm node process is successfully demonstrated. In order to obtain sufficiently large process windows, structures are printed larger than the designed target CD. As a consequence, a shrink of the structures needs to be applied to obtain the target CD after etch. Different shrink approaches are compared. Final results on wafer are discussed, focusing on critical layers as IM1, IM2, Via0 and Metal1.

Proceedings Article | 13 March 2012 Paper

Interactions between imaging layers during LPLE double patterning lithography

Stewart Robertson, Patrick Wong, Peter De Bisschop, Nadia Vandenbroeck, Vincent Wiaux

Proceedings Volume 8326, 83260B (2012) https://doi.org/10.1117/12.918058

KEYWORDS: Finite element methods, Photoresist processing, Double patterning technology, Diffusion, Lithography, Critical dimension metrology, Data modeling, Thermal modeling, Refractive index, Refraction

Read Abstract +

Proceedings Article | 23 March 2011 Paper

Spacer defined double patterning for (sub-)20nm half pitch single damascene structures

Janko Versluijs, Yong Kong Siew, Eddy Kunnen, Diziana Vangoidsenhoven, Steven Demuynck, Vincent Wiaux, Harold Dekkers, Gerald Beyer

Proceedings Volume 7973, 79731R (2011) https://doi.org/10.1117/12.881600

KEYWORDS: Etching, Double patterning technology, Semiconducting wafers, Optical lithography, Optical alignment, Line edge roughness, Carbon, Scanning electron microscopy, Line width roughness, Oxides

Read Abstract +

Proceedings Article | 23 March 2011 Paper

Mandrel-based patterning: density multiplication techniques for 15nm nodes

Chris Bencher, Huixiong Dai, Liyan Miao, Yongmei Chen, Ping Xu, Yijian Chen, Shiany Oemardani, Jason Sweis, Vincent Wiaux, Jan Hermans, Li-Wen Chang, Xinyu Bao, He Yi, H.-S. Philip Wong

Proceedings Volume 7973, 79730K (2011) https://doi.org/10.1117/12.881679

KEYWORDS: Optical lithography, Photomasks, Line width roughness, Lithography, Semiconducting wafers, Back end of line, Double patterning technology, Logic, Extreme ultraviolet, Directed self assembly

Read Abstract +

Proceedings Article | 23 March 2011 Paper

Characterization of a 'thermal freeze' litho-litho-etch (LLE) process for predictive simulation

Stewart Robertson, Patrick Wong, John Biafore, Mark Smith, Nadia Vandenbroeck, Vincent Wiaux

Proceedings Volume 7973, 79730L (2011) https://doi.org/10.1117/12.879508

KEYWORDS: Data modeling, Photoresist processing, Calibration, Thermal modeling, Double patterning technology, Finite element methods, Photoresist materials, Process modeling, Scanning electron microscopy, Wafer-level optics

Read Abstract +

Proceedings Article | 10 March 2010 Paper

Printing the metal and contact layers for the 32- and 22-nm node: comparing positive and negative tone development process

L. Van Look, J. Bekaert, V. Truffert, V. Wiaux, F. Lazzarino, M. Maenhoudt, G. Vandenberghe, Mario Reybrouck, Shinji Tarutani

Proceedings Volume 7640, 764011 (2010) https://doi.org/10.1117/12.848228

KEYWORDS: Printing, Photomasks, Scanning electron microscopy, Optical lithography, Etching, Semiconducting wafers, Lithography, Double patterning technology, Metals, Electroluminescence

Read Abstract +

Proceedings Article | 4 March 2010 Paper

Litho-process-litho for 2D 32nm hp Logic and DRAM double patterning

Patrick Wong, Vincent Wiaux, Staf Verhaegen, Nadia Vandenbroeck

Proceedings Volume 7640, 76400I (2010) https://doi.org/10.1117/12.846998

KEYWORDS: Double patterning technology, Thin film coatings, Optical lithography, Logic, Semiconducting wafers, Electroluminescence, Image processing, Line width roughness, Printing, Surface plasmons

Read Abstract +

SPIE Journal Paper | 1 July 2009

Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows

Kevin Lucas, Christopher Cork, Alexander Miloslavsky, Gerard Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Gregory Rollins, Vincent Wiaux, Staf Verhaegen

JM3, Vol. 8, Issue 03, 033002, (July 2009) https://doi.org/10.1117/12.10.1117/1.3158061

KEYWORDS: Semiconducting wafers, Double patterning technology, Lithography, Optical lithography, Etching, Photomasks, Optical proximity correction, Metals, Standards development, Critical dimension metrology

Read Abstract +

SPIE Journal Paper | 1 January 2009

30-nm half-pitch metal patterning using Motif^TM critical dimension shrink technique and double patterning

Janko Versluijs, Jean-Francois de Marneffe, Danny Goossens, Tom Vandeweyer, Vincent Wiaux, Herbert Struyf, Mireille Maenhoudt, Mohand Brouri, Johan Vertommen, Jisoo Kim, Helen Zhu

JM3, Vol. 8, Issue 01, 011007, (January 2009) https://doi.org/10.1117/12.10.1117/1.3066632

KEYWORDS: Etching, Critical dimension metrology, Optical lithography, Optical proximity correction, Metals, Scanning electron microscopy, Semiconducting wafers, Photomasks, Double patterning technology, Tin

Read Abstract +

Proceedings Article | 4 December 2008 Paper

A methodology for double patterning compliant split and design

Vincent Wiaux, Staf Verhaegen, Fumio Iwamoto, Mireille Maenhoudt, Takashi Matsuda, Sergei Postnikov, Geert Vandenberghe

Proceedings Volume 7140, 71401X (2008) https://doi.org/10.1117/12.804697

KEYWORDS: Double patterning technology, Optical lithography, Optical proximity correction, Logic, Metals, Photomasks, Etching, Failure analysis, Resolution enhancement technologies, Critical dimension metrology

Read Abstract +

Proceedings Article | 17 October 2008 Paper

Printability verification for double-patterning technology

Gerard Luk-Pat, Petrisor Panaite, Kevin Lucas, Christopher Cork, Vincent Wiaux, Staf Verhaegen, Mireille Maenhoudt

Proceedings Volume 7122, 71220Q (2008) https://doi.org/10.1117/12.801545

KEYWORDS: Etching, Lithography, Printing, Double patterning technology, Optical proximity correction, Critical dimension metrology, Resolution enhancement technologies, Scanning electron microscopy, Bridges, Extreme ultraviolet

Read Abstract +

Proceedings Article | 17 October 2008 Paper

Double-patterning decomposition, design compliance, and verification algorithms at 32nm hp

Alexander Tritchkov, Petr Glotov, Sergiy Komirenko, Emile Sahouria, Andres Torres, Ahmed Seoud, Vincent Wiaux

Proceedings Volume 7122, 71220S (2008) https://doi.org/10.1117/12.801381

KEYWORDS: Double patterning technology, Photomasks, Resolution enhancement technologies, Optical proximity correction, Optical lithography, Logic, Photoresist processing, Etching, Computer aided design, Silicon

Read Abstract +

Proceedings Article | 1 April 2008 Paper

30nm half-pitch metal patterning using Moti CD shrink technique and double patterning

Janko Versluijs, J.-F. De Marneffe, Danny Goossens, Maaike Op de Beeck, Tom Vandeweyer, Vincent Wiaux, Herbert Struyf, Mireille Maenhoudt, Mohand Brouri, Johan Vertommen, Ji Soo Kim, Helen Zhu, Reza Sadjadi

Proceedings Volume 6924, 69242C (2008) https://doi.org/10.1117/12.774139

KEYWORDS: Etching, Optical proximity correction, Optical lithography, Double patterning technology, Photomasks, Scanning electron microscopy, Semiconducting wafers, Metals, Tin, Dielectrics

Read Abstract +

Proceedings Article | 1 April 2008 Paper

Split and design guidelines for double patterning

Vincent Wiaux, Staf Verhaegen, Shaunee Cheng, Fumio Iwamoto, Patrick Jaenen, Mireille Maenhoudt, Takashi Matsuda, Sergei Postnikov, Geert Vandenberghe

Proceedings Volume 6924, 692409 (2008) https://doi.org/10.1117/12.774104

KEYWORDS: Double patterning technology, Optical lithography, Logic, Optical proximity correction, Photomasks, Metals, Etching, Failure analysis, Immersion lithography, Image resolution

Read Abstract +

Proceedings Article | 20 March 2008 Paper

Interactions of double patterning technology with wafer processing, OPC and design flows

Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Greg Rollins, Vincent Wiaux, Staf Verhaegen

Proceedings Volume 6924, 692403 (2008) https://doi.org/10.1117/12.778267

KEYWORDS: Semiconducting wafers, Optical lithography, Photomasks, Double patterning technology, Lithography, Etching, Metals, Optical proximity correction, 193nm lithography, Standards development

Read Abstract +

Proceedings Article | 12 March 2008 Paper

Checking design conformance and optimizing manufacturability using automated double patterning decomposition

Chris Cork, Brian Ward, Levi Barnes, Ben Painter, Kevin Lucas, Gerry Luk-Pat, Vincent Wiaux, Staf Verhaegen, Mireille Maenhoudt

Proceedings Volume 6925, 69251Q (2008) https://doi.org/10.1117/12.774647

KEYWORDS: Double patterning technology, Manufacturing, Optical lithography, Photomasks, Logic, Optical proximity correction, Ultraviolet radiation, Lithography, Semiconducting wafers, Phase shifts

Read Abstract +

Delays in equipment availability for both Extreme UV and High index immersion have led to a growing interest in double patterning as a suitable solution for the 22nm logic node. Double patterning involves decomposing a layout into two masking layers that are printed and etched separately so as to provide the intrinsic manufacturability of a previous lithography node with the pitch reduction of a more aggressive node. Most 2D designs cannot be blindly shrunk to run automatically on a double patterning process and so a set of guidelines for how to layout for this type of flow is needed by designers. While certain classes of layout can be clearly identified and avoided based on short range interactions, compliance issues can also extend over large areas of the design and are hard to recognize. This means certain design practices should be implemented to provide suitable breaks or performed with layout tools that are double patterning compliance aware. The most striking set of compliance errors result in layout on one of the masks that is at the minimum design space rather than the relaxed space intended. Another equally important class of compliance errors is that related to marginal printability, be it poor wafer overlap and/or poor process window (depth of focus, dose latitude, MEEF, overlay). When decomposing a layout the tool is often presented with multiple options for where to cut the design thereby defining an area of overlap between the different printed layers. While these overlap areas can have markedly different topologies (for instance the overlap may occur on a straight edge or at a right angled corner), quantifying the quality of a given overlap ensures that more robust decomposition solutions can be chosen over less robust solutions. Layouts which cannot be decomposed or which can only be decomposed with poor manufacturability need to be highlighted to the designer, ideally with indications on how best to resolve this issue. This paper uses an internally developed automated double pattern decomposition tool to investigate design compliance and describes a number of classes of non-conforming layout. Tool results then provide help to the designer to achieve robust design compliant layout.

Proceedings Article | 26 March 2007 Paper

Manufacturability issues with double patterning for 50-nm half-pitch single damascene applications using RELACS shrink and corresponding OPC

Maaike Op de Beeck, Janko Versluijs, Vincent Wiaux, Tom Vandeweyer, Ivan Ciofi, Herbert Struyf, Dirk Hendrickx, Jan Van Olmen

Proceedings Volume 6520, 65200I (2007) https://doi.org/10.1117/12.713393

KEYWORDS: Etching, Optical proximity correction, Photomasks, Double patterning technology, Semiconducting wafers, Photoresist processing, Atrial fibrillation, Optical lithography, Dielectrics, Scanning electron microscopy

Read Abstract +

Proceedings Article | 21 March 2007 Paper

Double pattern EDA solutions for 32nm HP and beyond

George Bailey, Alexander Tritchkov, Jea-Woo Park, Le Hong, Vincent Wiaux, Eric Hendrickx, Staf Verhaegen, Peng Xie, Janko Versluijs

Proceedings Volume 6521, 65211K (2007) https://doi.org/10.1117/12.712773

KEYWORDS: Double patterning technology, Photomasks, Optical proximity correction, Optical lithography, Metals, Electronic design automation, Etching, Manufacturing, Logic, Image processing

Read Abstract +

The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET). One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an optical extension [1]. The theoretical k₁ for a double-patterning technique of a 32nm half-pitch (HP) design for a 1.35NA 193nm imaging system is 0.44 whereas the k₁ for a single-exposure technique of this same design would be 0.22 [2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and OPC without encountering mask constraints. Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of DP requires the evolution and adoption of design restrictions by specifically tailored design rules. The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a production environment. As with any dual-mask RET application, there are the classical overlay requirements between the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration. For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go beyond this with the coupling of their model-based and process-window applications. This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA solutions were further analyzed and quantified utilizing a verification flow.

Proceedings Article | 21 March 2007 Paper

Double patterning design split implementation and validation for the 32nm node

Martin Drapeau, Vincent Wiaux, Eric Hendrickx, Staf Verhaegen, Takahiro Machida

Proceedings Volume 6521, 652109 (2007) https://doi.org/10.1117/12.712139

KEYWORDS: Double patterning technology, Optical lithography, Process control, Lithography, Logic, Optical proximity correction, Photomasks, Etching, Image processing, Immersion lithography

Read Abstract +

Proceedings Article | 20 October 2006 Paper

Application challenges with double patterning technology (DPT) beyond 45 nm

Jungchul Park, Stephen Hsu, Douglas Van Den Broeke, J. Fung Chen, Mircea Dusa, Robert Socha, Jo Finders, Bert Vleeming, Anton van Oosten, Peter Nikolsky, Vincent Wiaux, Eric Hendrickx, Joost Bekaert, Geert Vandenberghe

Proceedings Volume 6349, 634922 (2006) https://doi.org/10.1117/12.692921

KEYWORDS: Photomasks, Optical lithography, Optical proximity correction, Double patterning technology, Etching, Model-based design, Printing, Manufacturing, Critical dimension metrology, Photoresist processing

Read Abstract +

Proceedings Article | 30 September 2005 Paper

Silicon-on-insulator nanophotonics

Wim Bogaerts, Pieter Dumon, Patrick Jaenen, Johan Wouters, Stephan Beckx, Vincent Wiaux, Dries Van Thourhout, Dirk Taillaert, Bert Luyssaert, Roel Baets

Proceedings Volume 5956, 59560R (2005) https://doi.org/10.1117/12.624493

KEYWORDS: Waveguides, Photonic crystals, Nanophotonics, Silicon, Resonators, Oxides, Lithography, Polarization, Etching, Refractive index

Read Abstract +

Proceedings Article | 12 May 2005 Paper

Mask enhancer technology for 45-nm node contact hole fabrication

Takashi Yuito, Vincent Wiaux, Lieve Van Look, Geert Vandenberghe, Shigeo Irie, Takahiro Matsuo, Akio Misaka, Hisashi Watanabe, Masaru Sasago

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.598977

KEYWORDS: Thin films, Photomasks, Transmittance, Printing, Lithography, Halftones, Semiconducting wafers, Critical dimension metrology, Quartz, Resolution enhancement technologies

Read Abstract +

Proceedings Article | 5 May 2005 Paper

Optical extensions integration for a 0.314-µm² 45-nm node 6-transistor SRAM cell

Staf Verhaegen, Axel Nackaerts, Vincent Wiaux, Eric Hendrickx, Geert Vandenberghe

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600862

KEYWORDS: Integrated optics, Lithography, Resolution enhancement technologies, Microelectronics, Manufacturing, Printing, Scanners, Fiber optic illuminators, Lithographic illumination, Double patterning technology

Read Abstract +

A target of the 45nm node development at IMEC is to produce a working 6-transistor SRAM (6-T SRAM) cell. Here we describe the lithographic solutions for this challenge. Following the requirements of the ITRS Roadmap requires challenging k₁ values. A classical 6-transistor SRAM design is difficult to scale to lower k1 values for imaging and overlay reasons. In this paper we discuss the litho friendly design that was used to originally produce a working 0.314μm² 45nm node 6-transistor SRAM cell. The design was scaled to a k₁ value of 0.31 for printing the active area layer on a 0.75NA ArF scanner at IMEC. Later on this was further scaled to a k₁ of 0.280 and a cell size of 0.274μm² for a working cell and imaging with a k₁ of 0.265 on a higher NA tool. Various resolution enhancement techniques have been used for the three most critical layers of the SRAM cell: active area, poly gates and contact holes. Although designed unidirectional, the active area and the poly layer of the SRAM cell have critical features in two directions and therefore choosing the right illuminator shape is not straightforward. A pupil shape optimizer was used to maximize the contrast of the aerial image of the various critical features in these layers. For the contact layer the minimal pitch in the design is 160nm, which corresponds to a k₁ of 0.31. The pattern was split up into two images to increase the minimum pitch for the imaging to 190nm. Since off-axis illumination is used to print the 190nm pitch, assist features are added to the more sparse features. Contacts are not placed on a regular rectangular grid and additionally non-square contacts are used for local interconnects. This complicates the placement of the assist features and the interference mapping lithography (IML) technology was used to help in this task. The split design has been used in a double patterning approach in the SRAM process flow. In this paper we show that all the above-mentioned resolution enhancement techniques have been successfully integrated and that it resulted in a working 45nm node SRAM cell.

Proceedings Article | 15 September 2004 Paper

Low-loss photonic wires and compact ring resonators in silicon-on-insulator

Pieter Dumon, Wim Bogaerts, Joris Van Campenhout, Vincent Wiaux, Johan Wouters, Stephan Beckx, Roel Baets

Proceedings Volume 5450, (2004) https://doi.org/10.1117/12.548266

KEYWORDS: Resonators, Waveguides, Silicon, Wave propagation, Polarization, Photonic crystals, Silica, Dispersion, Lithography, Photonic integrated circuits

Read Abstract +

Proceedings Article | 20 August 2004 Paper

Through-pitch low-k₁ contact hole imaging with CPL technology

Vincent Wiaux, Joost Bekaert, J. Fung Chen, Stephen Hsu, Kurt Ronse, Robert Socha, Geert Vandenberghe, Douglas Van Den Broeke

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557803

KEYWORDS: Reticles, Resolution enhancement technologies, Printing, Lithography, Immersion lithography, Chromium, Electroluminescence, Semiconducting wafers, Photomasks, Critical dimension metrology

Read Abstract +

SPIE Journal Paper | 1 April 2004

Comparisons of 9% versus 6% transmission attenuated phase shift mask for the 65 nm device node

Patrick Montgomery, Lloyd Litt, Willard Conley, Kevin Lucas, Johannes van Wingerden, Geert Vandenberghe, Vincent Wiaux

JM3, Vol. 3, Issue 02, (April 2004) https://doi.org/10.1117/12.10.1117/1.1669524

KEYWORDS: Photomasks, Printing, Critical dimension metrology, Lithography, Phase shifts, Optical lithography, Metals, Nanoimprint lithography, Semiconducting wafers, Image transmission

Read Abstract +

Proceedings Article | 17 December 2003 Paper

Comparisons of 9% versus 6% transmission attenuated phase-shift mask for the 65-nm device mode

Patrick Montgomery, Kevin Lucas, Lloyd Litt, Will Conley, Eric Fanucchi, Johannes Van Wingerden, Geert Vandenberghe, Vincent Wiaux, Darren Taylor, Michael Cangemi, Bryan Kasprowicz

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518022

KEYWORDS: Photomasks, Inspection, Printing, Reticles, Critical dimension metrology, Optical lithography, Manufacturing, Metals, 193nm lithography, Nanoimprint lithography

Read Abstract +

Proceedings Article | 20 October 2003 Paper

Large-scale production techniques for photonic nanostructures

Wim Bogaerts, Vincent Wiaux, Pieter Dumon, Dirk Taillaert, Johan Wouters, Stephan Beckx, Joris Van Campenhout, Bert Luyssaert, Dries Van Thourhout, Roel Baets

Proceedings Volume 5225, (2003) https://doi.org/10.1117/12.503665

KEYWORDS: Photonic crystals, Waveguides, Silicon, Etching, Oxides, Lithography, Nanophotonics, Deep ultraviolet, Semiconducting wafers, Photomasks

Read Abstract +

Proceedings Article | 26 June 2003 Paper

Mighty high-T lithography for 65-nm generation contacts

Will Conley, Patrick Montgomery, Kevin Lucas, Lloyd Litt, John Maltabes, Laurent Dieu, Gregory Hughes, David Mellenthin, Robert Socha, Eric Fanucchi, Arjan Verhappen, Kurt Wampler, Linda Yu, Erika Schaefer, Shawn Cassel, Jan Kuijten, Wil Pijnenburg, Vincent Wiaux, Geert Vandenberghe

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485499

KEYWORDS: Photomasks, Lithography, Inspection, Reticles, Optical lithography, Lithographic illumination, Binary data, Manufacturing, 193nm lithography, Semiconducting wafers

Read Abstract +

Proceedings Article | 26 June 2003 Paper

ArF solutions for low-k₁ back-end imaging

Vincent Wiaux, Patrick Montgomery, Geert Vandenberghe, Philippe Monnoyer, Kurt Ronse, Will Conley, Lloyd Litt, Kevin Lucas, Jo Finders, Robert Socha, Douglas Van Den Broeke

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485502

KEYWORDS: Electroluminescence, Printing, Resolution enhancement technologies, Photomasks, Lithography, Reticles, Optical lithography, Phase shifts, Lithographic illumination, Metrology

Read Abstract +

The requirements stated in the ITRS roadmap for back-end-of-line imaging of current and future technology nodes are very aggressive. Therefore, it is likely that high NA in combination with enhancement techniques will be necessary for the imaging of contacts and trenches, pushing optical lithography into the low-k₁ regime. In this paper, we focus more specifically on imaging solutions for contact holes beyond the 90 nm node using high NA ArF lithography, as this is currently seen as one of the major challenges in optical lithography. We investigate the performance of various existing enhancement techniques in order to provide contact holes imaging solutions in a k₁ range from 0.35 to 0.45, using the ASML PAS5500/1100 0.75NA ArF scanner installed at IMEC. For various resolution enhancement techniques (RET), the proof of concept has been demonstrated in literature. In this paper, we propose an experimental one-to-one comparison of these RET’s with fixed CD target, exposure tool, lithographic process, and metrology. A single exposure through pitch (dense through isolated) printing solution is preferred and is the largest challenge. The common approach using a 6% attenuated phase-shifted mask (attPSM) with a conventional illumination fails. The advantages and drawbacks of other techniques are discussed. High transmission (17%) attenuated phase shift, potentially beneficial for part of the pitch range, requires conflicting trade-offs when looking for a single exposure through pitch solution. More promising results are obtained combining a BIM or a 6% attPSM with assist slots and off-axis illumination, yielding a depth of focus (DOF) at 8% exposure latitude (EL) greater than 0.31 μm from 200 nm pitch through isolated. Chromeless phase lithography (CPL) is also discussed with promising results obtained at the densest pitch. At a 0.4 k₁, an experimental extrapolation to 0.85NA demonstrates that a pitch of 180 nm can be resolved with 0.4 μm DOF at 8% EL. For all of these imaging solutions, various metrics are studied to compare printing performance. In addition to process latitude, we consider forbidden pitches, sidelobes printability, and mask error enhancement factor (MEEF).

Proceedings Article | 26 June 2003 Paper

Process, design, and optical proximity correction requirements for the 65nm device generation

Kevin Lucas, Patrick Montgomery, Lloyd Litt, Will Conley, Sergei Postnikov, Wei Wu, Chi-Min Yuan, Marc Olivares, Kirk Strozewski, Russell Carter, James Vasek, David Smith, Eric Fanucchi, Vincent Wiaux, Geert Vandenberghe, Olivier Toublan, Arjan Verhappen, Jan Kuijten, Johannes van Wingerden, Bryan Kasprowicz, Jeffrey Tracy, Christopher Progler, Eugene Shiro, Igor Topouzov, Karl Wimmer, Bernard Roman

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485498

KEYWORDS: Reticles, Optical lithography, Optical proximity correction, Lithography, 193nm lithography, Scanners, Logic, Optical design, Lithographic illumination, SRAF

Read Abstract +

Proceedings Article | 16 August 2002 Paper

OPC aware mask and wafer metrology

Wilhelm Maurer, Vincent Wiaux, Rik Jonckheere, Vicky Philipsen, Thomas Hoffmann, Staf Verhaegen, Kurt Ronse, Jonathan England, William Howard

Proceedings Volume 4764, (2002) https://doi.org/10.1117/12.479350

KEYWORDS: Optical proximity correction, Photomasks, Lithography, Metrology, Image processing, Scanning electron microscopy, Semiconducting wafers, Image analysis, Transistors, Line edge roughness

Read Abstract +

Proceedings Article | 30 July 2002 Paper

Assessment of OPC effectiveness using two-dimensional metrics

Vincent Wiaux, Vicky Philipsen, Rik Jonckheere, Geert Vandenberghe, Staf Verhaegen, Thomas Hoffmann, Kurt Ronse, William Howard, Wilhelm Maurer, Moshe Preil

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474588

KEYWORDS: Reticles, Optical proximity correction, Photomasks, Scanning electron microscopy, Semiconducting wafers, Critical dimension metrology, Optical lithography, Metrology, Printing, Logic

Read Abstract +

A complete evaluation of the optical proximity effects (OPE) and of their corrections (OPC) requires a quantitative description of two-dimensional (2D) parameters, both at resist- and at reticle-level. Because the 2D behaviour at line-ends and at line-corners can become a limiting factor for the yield, it should be taken into account when characterising a process, just as the CD- and pitch-linearity are already kept under control. This implies the measurement of 2D-metrics in a precise way. We used an SEM Image Analysis tool (ProDATA SIAM) to define and measure various OPC-relevant metrics for a C013 process. For the METAL (M1) process, we show that the overlap between line-ends of M1-trenches and underlying nominal contacts is a relevant metric to describe the effectiveness of hammerheads. Moreover, it is an interesting metric to combine with the CD process window. For the GATE process, we demonstrate that for a given set of metrics there is a degree of OPC aggressiveness beyond which it is not worth to go. We considered both line-end shortening (LES) and corner rounding affecting the poly linewidth close to a contact pad, and this on various logic circuits having received different degrees of fragmentation. Finally the knowledge of the actual line-end contour on the reticle allows one to simulate separately the printing effect of that area loss at reticle line-ends. The area loss measured by comparing the extracted contour to the target one is regarded as a combination of pull-back and area loss at corners. For our C013 gate process, and for the 130nm lines at a 1:1.25 duty cycle, those two parameters contribute together to approximetely 40% of the measured LES in the resist. This fact raises the question of specifications on 2D reticle parameters. We also find a linear correlation between the area loss at reticle line-end corners and the corresponding increase of LES on the wafer, which suggests a way towards putting specifications on the reticle line-ends.

Proceedings Article | 30 July 2002 Paper

Tuning and simulating a 193-nm resist for 2D applications

William Howard, Vincent Wiaux, Monique Ercken, Bang Bui, Jeff Byers, Mike Pochkowski

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474499

KEYWORDS: Photomasks, Semiconducting wafers, Scanning electron microscopy, Optical proximity correction, Metrology, Reticles, Finite element methods, Data modeling, Lithography, 3D image processing

Read Abstract +

Proceedings Article | 5 September 2001 Paper

Reticle quality needs for advanced 193-nm lithography

Rik Jonckheere, Geert Vandenberghe, Vincent Wiaux, Staf Verhaegen, Kurt Ronse

Proceedings Volume 4409, (2001) https://doi.org/10.1117/12.438345

KEYWORDS: Photomasks, Optical proximity correction, Reticles, Semiconducting wafers, Printing, 193nm lithography, Critical dimension metrology, Metrology, Lithography, Optical lithography

Read Abstract +

Showing 5 of 56 publications

Conference Committee Involvement (1)

Photomask Technology

18 September 2007 | Monterey, California, United States

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years