Dark field Alternating Aperture Phase Shift Mask (AAPSM) technology has developed into an enabling Resolution Enhancement Technology (RET) in the sub-100nm semiconductor device era. As phase shift masks are increasingly used to resolve features beyond just the most critical (for example transistor gates on the poly layer) the probability of phase conflicts (same phase across a feature) has increased tremendously. It has become imperative to introduce design practices that enable the semiconductor fabrication to take advantage of the improved performance that AAPSM delivers. In this paper we analyze the different causes for phase conflicts and the appropriate methods for detecting them, thus building the basis for the Hybrid AAPSM compliance flow. This approach leverages the strengths of existing DRC tools and the AAPSM conversion software. The approach is effective for minimizing the area penalty, thus very effective for density driven designs. By design, it is suited for custom or semi-custom layouts.
KEYWORDS: Phase shifts, System on a chip, Semiconductors, Optical proximity correction, Photomasks, Commercial off the shelf technology, Image enhancement, Transistors, Logic, Manufacturing
As the semiconductor industry has began production of subwavelength geometries, technologies such as Optical Proximity Correction (OPC) and Phase-Shifting Masks (PSM) have become requirements in producing integrated circuits. One of these approaches, Alternating PSM (AltPSM), has been adopted by leading edge semiconductor companies to meet IC manufacturing production requirements. As part of a complete production flow for these processes, it is required for SOC IP to be "phase compliant". Only through the phase compliance, the fabless COT semiconductor market is enabled to leverage the benefits of subwavelength geometries. This paper introduces the concept of phase compliance, and the importance of guaranteeing correct phase topology and phase compliance of layouts for AltPSM. It further proposes a method to create phase compliant SoC IP, and a process of verifying that SoC IP is phase compliance. The timing characterizaitn data is also included to show that the performance speed of the memory layouts was enhanced by 20% over regular 0.13 micron proces. The paper concludes with some general remarks on how this methodolgy will be impacted as we move to 65nm node.
The X Architecture is a novel on-chip interconnect architecture based on the pervasive use of diagonal wiring. This diagonal wiring reduces total chip wire length by an average 20% and via count by an average of 30%, resulting in simultaneous improvements in chip speed, power, a cost. Thirty percent or greater reduction in via counts is a compelling feature for IC design - but can chips with massive amounts of diagonal wiring be manufactured without some other penalty? This paper presents the result of a project, collaborated by Cadence Design Systems, Numerical Technologies, DuPont Photomasks, and Nikon, aimed at optimizing each step of the lithography supply chain for the Architecture from masks to wafers at 130 nm.
The emerging demand for smaller and smaller IC features, undiminished by the delay of next generation stepper technologies, has increased the need for OPC and PSM designs that are becoming critical for leading-edge IC manufacturing. However, modifications made to the original layout by OPC or PSM deign tools in general, exclude the use of conventional design verification tools to verify the modified designs. Therefore, the question of design 'correctness' often goes unanswered until after the wafers have been printed. This is extremely costly in terms of time and money. In this paper, we address the critical issue that has thus far remained open, the development of methods for physical verification of OPC designs. Our approach uses fast lithography simulation to map the modified mask design to the final patterns produced on the wafer. The simulated wafer pattern is matched against the specified tolerances and the problem areas are reported. It is a hierarchical verification tool. The hierarchical processing of the data makes it a high performance tool and keeps the data volume in check. We validate this technology by comparing the simulation results with the experimental data. In addition, performance measurements indicate that it is an effective and practical solution to the problem of verifying correctness of full-chip OPC designs.
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