Subwavelength lithography at low contrast, or low-k1 factor, leads to new requirements for design, design analysis, and design verification techniques. These techniques must account for inherent physical circuit feature distortions resulting from layout pattern-dependent design-to-silicon patterning processes in this era. These
distortions are unavoidable, even in the presence of sophisticated Resolution Enhancement Technologies (RET), and are a 'fact-of-life’ for the designer implementing nanometer-scale designs for the foreseeable low-k1 future. The consequence is that fabricated silicon feature shapes and dimensions are in general printed with far less
fidelity in comparison to the designer’s desired layout than in past generations and that the designer must consider design within significantly different margins of geometry tolerance. Traditional (Mead-Conway originated) WYSIWYG (what you see is what you get) design methodologies, assume that the designer’s physical circuit element shapes are accurate in comparison to the corresponding shapes on the real fabricated IC, and uses design rules to verify satisfactory fabrication compliance, as the input for both
interconnect parasitic loading calculations and to transistor models used for performance simulation. However, these assumptions are increasingly poor ones as k1 decreases to unprecidented levels -- with concomitant increase in patterned feature distortion and fabrication yield failure modes. This paper explores a new paradigm for nanometer-scale design, one in which more advanced models of critical low-k1 lithographic printing effects are incorporated into the design flow to improve upon yield and performance verification accuracy. We start with an analysis of a complex 32-bit adder block circuit design to determine systematic changes in gate length, width and shape variations for each MOSFET in the circuit due to optical
proximity effects. The physical gate dimensions for all, as predicted by the simulations, are then incorporated into the circuit simulation models and netlist (schematic) and are used to calculate the changes in critical parametric yield factors such as timing and power consumption in the circuit behavior. These functional consequences create a manufacturability tolerance requirement that relates to function and parametric yield, not just physical manufacturability. We then explore the improvements in functional attributes and manufacturability that arise from systematic correction of these distortions by RET including; simulation-driven model-based OPC,
alternating-aperture PSM (altPSM), and altPSM+OPC. This analysis is just one dimension of a systmatic methodology that incorporates lithographic effects into a design for manufacturing (DFM) scheme. The benefits promise dramatically improved silicon-signoff verification, predictive performance and yield analysis, and more
cost-effective application of RET.
Dramatically increasing mask set costs, long-loop design-fabrication iterations, and lithography of unprecedented complexity and cost threaten to disrupt time-accepted IC industry progression as described by Moore’s Law. Practical and cost-effective IC manufacturing below the 100nm technology node presents significant and unique new challenges spanning multiple disciplines and overlapping traditionally separable components of the design-through-chip manufacturing flow. Lithographic and other process complexity is compounded by design, mask, and infrastructure technologies, which do not sufficiently account for increasingly stringent and complex manufacturing issues. Deep subwavelength and atomic-scale process and device physics effects increasingly invade and impact the design flow strongly at a time when the pressures for increased design productivity are escalating at a superlinear rate. Productivity gaps, both upstream in design and downstream in fabrication, are anticipated by many to increase due to dramatic increases in inherent complexity of the design-to-chip equation.
Furthermore, the cost of lithographic equipment is increasing at an aggressive compound growth rate so large that we can no longer economically derive the benefit of the increased number of circuits per unit area unless we extend the life of lithographic equipment for more generations, and deeper into the subwavelength regime.
Do these trends unambiguously lead to the conclusion that we need a revolution in design and design-process integration to enable the sub-100nm nodes? Or is such a premise similar to other well-known predictions of technology brick walls that never came true?
In this paper, we discuss rule-based and model-based tiling methodologies for interconnect layers and their implications for design flows and performance. The addition of these 'dummy' tiling metal features modifies the final physical design and reduces the variation of back-end process parameters. This is a newly developing area of design flow and its importance is increasing with each succeeding semiconductor generation. Along with this development new methodologies and tools need to be introduced to handle time placement post-physical design, as well as efficient methods for representing the resulting large amount of dat. Additionally, the inclusion of tiles may introduce performance-degrading parasitic effects. The situation is complicated by the order of the elements of the design flow: parasitics characterization requires knowledge about the placement of dummy metal times, which takes place after physical design. In this study, we co pare the advantages of having uniform interconnect characteristics to the performance degradation caused by the additional layout parasitics. We also discuss several possible scenarios for the modification of design flows to account for these effects the thereby recover timing and power targets closure. These scenarios depend for their success on the very different length scales of polish and electromagnetic effects. Finally, an analysis of correlations in the parameters that define design corners leads to the new conclusion that the negative effect of increased parasitic loading due to tiling is not as sever as a simple analysis would suggest. This result is due to the fact that the tiling parasitic loading is somewhat compensated for by the improved planarity resulting from tiling, which tightens the process variation-induced spread of metal electrical parameters.
In recent years mask data preparation (MDP) has been complicated by a number of factors, including the introduction of resolution enhancement technologies such as optical proximity correction (OPC) and phase shift masks. These complications not only have led to significant increases in file sizes and computer runtimes, but they have also created an urgent need for data management tools -- MDP automation. Current practices rely on point solutions to specific problems, such as OPC; use outdated, proprietary, non-standard, informal or inefficient data formats; and just barely manage portions of the data flow via low-level scripting. Without automation, MDP requires human intervention, which leads to longer cycle times and more errors. Without adequate data interchange formats, automation cannot succeed. This paper examines MDP processes and data formats, and suggests opportunities for improvement. Within the context of existing data formats, we examine the effect of inadequate (e.g., proprietary) data formats on MDP flow. We also examine the closest thing to an open, formal, standard data format--GDSII--and suggest improvements and even a replacement based on the extensible markup language (XML).
In this paper we introduce the concept and design of a novel phase shift mask technology, Polarized Phase Shift Mask (P:PSM). The P:PSM technology utilizes non-interference between orthogonally polarized light sources to avoid undesired destructive interference seen in conventional two-phase shift mask technology. Hence P:PSM solves the well-known 'phase edge' or 'phase conflict' problem. By obviating the 2nd exposure and 2nd mask in current Complementary Phase Shift Mask (C:PSM) technology, this single mask/single exposure technology offers significant advantages towards photolithography process as well as pattern design. We use examples of typical design and process difficulties associated with the C:PSM technology to illustrate the advantages of the P:PSM technology. We present preliminary aerial image simulation results that support the potential of this new reticle technology for enhanced design flexibility. We also propose possible mask structures and manufacturing methods for building a P:PSM.
Simplified 2-D Optical Proximity Correction (OPC) algorithms have been devised, calibrated and implemented on a state-of- the-art 0.25 micrometer random logic process in order to reduce metal line pullback on critical layers. The techniques used are rules-based, but are characterized by fast and robust data conversion algorithms, calibrations based on actual process data improvements in reticle manufacturability, and inspectability of the resultant OPC corrected reticles. Application to local interconnect and metal patterning has corrected fundamental yield-limiting mechanisms in these levels.