Mr. Wayne H. Chang Profile

Wayne H. Chang

Technologist Research Scientist at Western Univ Canada

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Proceedings Article | 29 March 2006 Paper

ArF processing of 90-nm design rule lithography achieved through enhanced thermal processing

Markus Kagerer, Daniel Miller, Wayne Chang, Daniel Williams

Proceedings Volume 6153, 615333 (2006) https://doi.org/10.1117/12.659235

KEYWORDS: Semiconducting wafers, Temperature metrology, Control systems, Critical dimension metrology, Photoresist processing, Diffractive optical elements, Lithography, Control systems design, Data modeling, Wafer testing

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As the lithography community has moved to ArF processing on 300 mm wafers for 90 nm design rules the process characterization of the components of variance continues to highlight the thermal requirements for the post exposure bake (PEB) processing step. In particular as the thermal systems have become increasingly uniform, the transient behavior of the thermal processing system has received the focus of attention. This paper demonstrates how a newly designed and patented thermal processing system was optimized for delivering improved thermal uniformity during a typical 90 second PEB processing cycle, rather than being optimized for steady state performance. This was accomplished with the aid of a wireless temperature measurement wafer system for obtaining real time temperature data and by using a response surface model (RSM) experimental design for optimizing parameters of the temperature controller of the thermal processing system. The new units were field retrofitted seamlessly in <2 days at customer sites without disruption to process recipes or flows. After evaluating certain resist parameters such as PEB temperature sensitivity and post exposure delay (PED) - stability of the baseline process, the new units were benchmarked against the previous PEB plates by processing a split lot experiment. Additional hardware characterization included environmental factors such as air velocity in the vicinity of the PEB plates and transient time between PEB and chill plate. At the completion of the optimization process, the within wafer CD uniformity displayed a significant improvement when compared to the previous hardware. The demonstrated within wafer CD uniformity improved by 27% compared to the initial hardware and baseline process. ITRS requirements for the 90 nm node were exceeded.

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