Dr. William H. Robinson Profile

Dr. William H. Robinson

Assistant Professor of Electrical Engineering at Vanderbilt Univ

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Proceedings Article | 7 May 2003 Paper

Analysis of area-time efficiency for an integrated focal plane architecture

William Robinson, D. Scott Wills

Proceedings Volume 5022, (2003) https://doi.org/10.1117/12.476615

KEYWORDS: Image processing, Personal protective equipment, Digital signal processing, Analog electronics, Staring arrays, Signal processing, Digital filtering, Silicon, Array processing, Data storage

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Monolithic integration of photodetectors, analog-to-digital converters, digital processing, and data storage can improve the performance and efficiency of next-generation portable image products. Our approach combines these components into a single processing element, which is tiled to form a SIMD focal plane processor array with the capability to execute early image applications such as median filtering (noise removal), convolution (smoothing), and inside edge detection (segmentation). Digitizing and processing a pixel at the detection site presents new design challenges, including the allocation of silicon resources. This research investigates the area-time (A•T²) efficiency by adjusting the number of Pixels-per-Processing Element (PPE). Area calculations are based upon hardware implementations of components scaled for 250nm or 120nm technology. The total execution time is calculated from the sequential execution of each application on a generic focal plane architectural simulator. For a Quad-CIF system resolution (176×144), results show that 1 PPE provides the optimal area-time efficiency (5.7 μs² x mm² for 250nm, 1.7 μs² x mm² for 120nm) but requires a large silicon chip (2072mm² for 250nm, 614mm² for 120nm). Increasing the PPE to 4 or 16 can reduce silicon area by 48% and 60% respectively (120nm technology) while maintaining performance within real-time constraints.

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