Dr. William M. Tong Profile

Dr. William M. Tong

Researcher at Self

SPIE Involvement:

Author | Editor

Publications (16)

Proceedings Article | 28 March 2014 Paper

Paper

The REBL DPG: recent innovations and remaining challenges

Allen Carroll, Luca Grella, Kirk Murray, Mark McCord, Paul Petric, William Tong, Christopher Bevis, Shy-Jay Lin, Tsung-Hsin Yu, Tze-Chiang Huang, T. Wang, Wen-Chuan Wang, J. Shin

Proceedings Volume 9049, 904917 (2014) https://doi.org/10.1117/12.2048528

KEYWORDS: Mirrors, Lithography, Semiconducting wafers, Error control coding, Reflectivity, Switching, Electrodes, Data compression, Printing, Electron beam lithography

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SPIE Journal Paper | 30 September 2013 Open Access

Open Access

Special Section Guest Editorial: Alternative Lithographic Technologies

William Tong, Douglas Resnick, Ricardo Ruiz

JM3, Vol. 12, Issue 03, 031101, (September 2013) https://doi.org/10.1117/12.10.1117/1.JMM.12.3.031101

KEYWORDS: Lithography, High volume manufacturing, Extreme ultraviolet lithography, Optical lithography, Overlay metrology, Explosives, Metrology, Roads, Molecular self-assembly, Directed self assembly

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SPIE Journal Paper | 5 August 2013 Open Access

Open Access

Digital pattern generator: an electron-optical MEMS for massively parallel reflective electron beam lithography

Luca Grella, Allen Carroll, Kirk Murray, Mark McCord, William Tong, Alan Brodie, Thomas Gubiotti, Fuge Sun, Francoise Kidwingira, Shinichi Kojima, Paul Petric, Christopher Bevis, Bart Vereecke, Luc Haspeslagh, Anil Mane, Jeffrey Elam

JM3, Vol. 12, Issue 03, 031107, (August 2013) https://doi.org/10.1117/12.10.1117/1.JMM.12.3.031107

KEYWORDS: Electrodes, Mirrors, Microelectromechanical systems, Semiconducting wafers, Tin, Electron beam lithography, Metals, Aluminum, Coating, Reflectivity

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Proceedings Article | 26 March 2013 Paper

Paper

Reflective electron beam lithography: lithography results using CMOS controlled digital pattern generator chip

Thomas Gubiotti, Jeff Fuge Sun, Regina Freed, Francoise Kidwingira, Jason Yang, Chris Bevis, Allen Carroll, Alan Brodie, William Tong, Shy-Jay Lin, Wen-Chuan Wang, Luc Haspeslagh, Bart Vereecke

Proceedings Volume 8680, 86800H (2013) https://doi.org/10.1117/12.2010722

KEYWORDS: Semiconducting wafers, Electron beam lithography, Lithography, Coating, Logic, Electron beams, Polymethylmethacrylate, Printing, Reflectivity, Silica

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Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 10 nm logic (16 nm half pitch) technology node and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL) technology targeting high-volume 10 nm logic node performance. REBL uses a novel multi-column wafer writing system combined with an advanced stage architecture to enable the throughput and resolution required for a NGL system. Using a CMOS Digital Pattern Generator (DPG) chip with over one million microlenses, the system is capable of maskless printing of arbitrary patterns with pixel redundancy and pixel-by-pixel grayscaling at the wafer. Electrons are generated in a flood beam via a thermionic cathode at 50-100 keV and decelerated to illuminate the DPG chip. The DPG-modulated electron beam is then reaccelerated and demagnified 80-100x onto the wafer to be printed. Previously, KLA-Tencor reported on the development progress of the REBL tool for maskless lithography at and below the 10 nm logic technology node. Since that time, the REBL team has made good progress towards developing the REBL system and DPG for direct write lithography. REBL has been successful in manufacturing a CMOS controlled DPG chip with a stable charge drain coating and with all segments functioning. This DPG chip consists of an array of over one million electrostatic lenslets that can be switched on or off via CMOS voltages to pattern the flood electron beam. Testing has proven the validity of the design with regards to lenslet performance, contrast, lifetime, and pattern scrolling. This chip has been used in the REBL demonstration platform system for lithography on a moving stage in both PMMA and chemically amplified resist. Direct imaging of the aerial image has also been performed by magnifying the pattern at the wafer plane via a mag stack onto a YAG imaging screen. This paper will discuss the chip design improvements and new charge drain coating that have resulted in a functional DPG chip and will evaluate the current chip performance on the REBL system. Print results for line/space and device test patterns at the 100nm node will be presented.

SPIE Journal Paper | 9 August 2012 Open Access

Open Access

Special Section Guest Editorial: Alternative Lithographic Technologies

William Tong, Douglas Resnick, Benjamen Rathsack

JM3, Vol. 11, Issue 3, 031401, (August 2012) https://doi.org/10.1117/12.10.1117/1.JMM.11.3.031401

KEYWORDS: Lithography, Optical lithography, Explosives, Nanoimprint lithography, Semiconductor manufacturing, Semiconductors, Optics manufacturing, Immersion lithography, Double patterning technology, Directed self assembly

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Proceedings Article | 18 March 2009 Open Access

Open Access

Paper

On the integration of memristors with CMOS using nanoimprint lithography

Qiangfei Xia, W. Tong, W. Wu, J. Yang, X. Li, W. Robinett, T. Cardinali, M. Cumbie, J. Ellenson, P. Kuekes, R. S. Williams

Proceedings Volume 7271, 727106 (2009) https://doi.org/10.1117/12.814327

KEYWORDS: Nanoimprint lithography, Electrodes, Metals, Ultraviolet radiation, Reactive ion etching, Switching, Hybrid circuits, Optical lithography, CMOS technology, Nanowires

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Proceedings Article | 14 March 2008 Paper

Paper

Fabrication and test of nano crossbar switches/MOSFET hybrid circuits by imprinting lithography

Zhiyong Li, Xuema Li, Douglas Ohlberg, Joseph Straznicky, Wei Wu, Zhaoning Yu, Julien Borghetti, William Tong, Duncan Stewart, R. Stanley Williams

Proceedings Volume 6921, 692108 (2008) https://doi.org/10.1117/12.774144

KEYWORDS: Field effect transistors, Hybrid circuits, Lithography, Resistance, Integrated circuits, Logic, Silicon, Switches, Nanoimprint lithography, Nanowires

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Proceedings Article | 24 March 2006 Paper

Paper

nDSE-based overlay alignment: enabling technology for nanometrology and fabrication

Jun Gao, Carl Picciotto, Wei Wu, Inkyu Park, William Tong

Proceedings Volume 6152, 615223 (2006) https://doi.org/10.1117/12.656610

KEYWORDS: Optical alignment, Detection and tracking algorithms, Algorithm development, Semiconducting wafers, Algorithms, Overlay metrology, Image processing, Error analysis, Fourier transforms, Sensing systems

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Proceedings Article | 6 May 2005 Paper

Paper

Surface engineering for resolution enhancement in nanoimprint lithography

G. Y. Jung, W. Wu, Z. Li, S. Y. Wang, William Tong, R. Williams

Proceedings Volume 5751, (2005) https://doi.org/10.1117/12.599793

KEYWORDS: Nanoimprint lithography, Molecules, Lithography, Ultraviolet radiation, Scanning electron microscopy, Resolution enhancement technologies, Photoresist processing, Optical lithography, Capillaries, Nanowires

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Proceedings Article | 6 May 2005 Paper

Paper

Nanoimprint lithography: the path toward high-tech, low-cost devices

William Tong, Scott Hector, Gun-Young Jung, Wei Wu, James Ellenson, Kenneth Kramer, Timothy Hostetler, Susan Richards, R. Williams

Proceedings Volume 5751, (2005) https://doi.org/10.1117/12.607236

KEYWORDS: Photomasks, Nanoimprint lithography, Optical lithography, Inspection, Optical alignment, Extreme ultraviolet lithography, Nanotechnology, Electron beam lithography, Lithography, Semiconductor manufacturing

Read Abstract +

Nanoimprint lithography is a contact-lithography technology invented in 1996 as a low-cost alternative to photolithography for researchers who need high resolution patterning. Initially perceived as a trailing-edge technology for low-cost device fabrication, it has been recently demonstrated to achieve sub-10 nm resolution and alignment, which equal or surpass even the most advanced photolithography today. At Hewlett-Packard, we have successfully used it to fabricate switchable molecular memory arrays with a dimension of 65 nm half pitch. Nanoimprint has been placed on the International Technology Roadmap for Semiconductors (ITRS) as a candidate for next-generation lithography (NGL) for insertion in the 32 nm node in Y2013. The switch from using light to using contact to pattern will indeed bring new challenges, the most important of which are alignment and the 1x mask/template. For alignment, one imprint tool maker has achieved alignment of +/-7 nm 3 sigma using Moire patterns. For template fabrication, the lack of OPC and other sub-resolution features produced large savings in patterning, but it is nearly cancelled out by the need for more aggressive inspection because of the smaller tolerable defect size. The two combined to make the predicted cost of nanoimprint template to be similar to photomasks for 45-nm half pitch. At 32-nm half pitch, EUVL masks do not have complicated sub-resolution features and are predicted to be cheaper than comparable nanoimprint templates provided that the former’s defect levels can be reduced to what is required for economical manufacturing. In both cases, the challenges are not insurmountable and solutions are being actively pursued. However, if nanoimprint is indeed the disruptive technology to photolithography, it needs to take its initial aim at the low-end market rather than mount a frontal challenge at semiconductor manufacturing, which is the high-margin customers that photolithography will pursue and protect at all cost. The recent development in nanotechnology will lead to the commercialization of a new class of nanoscale devices requiring a high-resolution lithographic technique that does not have all the functionalities of photolithography. This approach will provide an initial customer base for nanoimprint to develop and improve and position it to challenge photolithography in the distant future.

Proceedings Article | 20 May 2004 Paper

Paper

Fabrication process of molecular memory circuits by nanoimprint lithography

Gun-Young Jung, S. Ganapathiappan, Xuema Li, Dougleas Ohlberg, Deidre Olynick, Yong Chen, Wei Wu, Shih-Yuan Wang, William Tong, R. Williams

Proceedings Volume 5374, (2004) https://doi.org/10.1117/12.540898

KEYWORDS: Electrodes, Nanoimprint lithography, Polymers, Titanium, Platinum, Polymer thin films, Polymethylmethacrylate, Lithography, Scanning electron microscopy, Nanowires

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Proceedings Article | 22 January 2001 Paper

Paper

Predictive model of the cost of extreme-ultraviolet lithography masks

Scott Hector, Patrick Kearney, Claude Montcalm, James Folta, Christopher Walton, William Tong, John Taylor, Pei-yang Yan, Charles Gwyn

Proceedings Volume 4186, (2001) https://doi.org/10.1117/12.410754

KEYWORDS: Photomasks, Extreme ultraviolet lithography, Multilayers, Inspection, Coating, Optical lithography, Lithography, Process modeling, Defect detection, Ion beams

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Proceedings Article | 21 July 2000 Paper

Paper

EUVL printing results of a low-thermal expansion material (LTEM) mask

William Tong, John Taylor, Scott Hector, Melissa Shell, Guojing Zhang, Patrick Kearney, Christopher Walton, Cindy Larson, James Wasson, Pawitter Mangat, Donna O'Connell, Daniel Folk

Proceedings Volume 3997, (2000) https://doi.org/10.1117/12.390038

KEYWORDS: Photomasks, Extreme ultraviolet lithography, Semiconducting wafers, Silicon, Manufacturing, Printing, Distortion, Lithography, Extreme ultraviolet, Reflectivity

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Proceedings Article | 30 December 1999 Paper

Paper

Mask substrate requirements and development for extreme ultraviolet lithography (EUVL)

William Tong, John Taylor, Scott Hector, Melissa Shell

Proceedings Volume 3873, (1999) https://doi.org/10.1117/12.373338

KEYWORDS: Photomasks, Extreme ultraviolet lithography, Semiconducting wafers, Silicon, Surface finishing, Distortion, Extreme ultraviolet, Chemical mechanical planarization, Printing, Atomic force microscopy

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Proceedings Article | 23 April 1999 Paper

Paper

Mask technology for EUV lithography

M. Bujak, Scott Burkhart, Charles Cerjan, Patrick Kearney, Craig Moore, Shon Prisbrey, Donald Sweeney, William Tong, Stephen Vernon, Christopher Walton, Abbie Warrick, Frank Weber, Marco Wedowski, Karl Wilhelmsen, Jeffrey Bokor, Sungho Jeong, Gregory Cardinale, Avijit Ray-Chaudhuri, Alan Stivers, Edita Tejnil, Pei-yang Yan, Scott Hector, Khanh Nguyen

Proceedings Volume 3665, (1999) https://doi.org/10.1117/12.346225

KEYWORDS: Photomasks, Extreme ultraviolet lithography, Semiconducting wafers, Multilayers, Reflectivity, Extreme ultraviolet, Silicon, Inspection, Optical lithography, Ion beams

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Proceedings Article | 30 July 1997 Paper

Paper

Core level spectroscopy for surface analysis

Franz Himpsel, R. Treusch, I. Jimenez, Alan Jankowski, D. Sutherland, L. Terminello, C. Heske, Rupert Perera, D. Shuh, William Tong, James Underwood, J. Carlisle, T. Callcott, Jian Jun Jia, David Ederer, Dieter Gruen, Alan Krauss, D. Zuiker, Gary Doll

Proceedings Volume 10291, 102910J (1997) https://doi.org/10.1117/12.279846

KEYWORDS: Spectroscopy, Chemical analysis, Photoemission spectroscopy, Absorption spectroscopy, X-ray fluorescence spectroscopy, Chemical species, Molecules, Oxidation, Nondestructive evaluation, Electrons

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Showing 5 of 16 publications

Proceedings Volume Editor (4)

SPIE Conference Volume | 11 April 2013

Alternative Lithographic Technologies V

SPIE Conference Volume | 18 April 2012

Alternative Lithographic Technologies IV

SPIE Conference Volume | 1 April 2011

Alternative Lithographic Technologies III

SPIE Conference Volume | 10 March 2010

Alternative Lithographic Technologies II

Conference Committee Involvement (8)

Alternative Lithographic Technologies VI

24 February 2014 | San Jose, California, United States

Alternative Lithographic Technologies V

25 February 2013 | San Jose, California, United States

Alternative Lithographic Technologies IV

13 February 2012 | San Jose, California, United States

Alternative Lithographic Technologies III

1 March 2011 | San Jose, California, United States

Alternative Lithographic Technologies II

23 February 2010 | San Jose, California, United States

Showing 5 of 8 Conference Committees

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