The Silicon-On-Insulator (SOI) CMOS is one of the most advanced and promising technology for monolithic pixel detectors design. The insulator layer that is implemented inside the silicon crystal allows to integrate sensors matrix and readout electronic on a single wafer. Moreover, the separation of electronic and substrate increases also the SOI circuits performance. The parasitic capacitances to substrate are significantly reduced, so the electronic systems are faster and consume much less power. The authors of this presentation are the members of international SOIPIX collaboration, that is developing SOI pixel detectors in 200 nm Lapis Fully-Depleted, Low-Leakage SOI CMOS. This work shows a set of advantages of SOI technology and presents possibilities for pixel detector design SOI CMOS. In particular, the preliminary results of a Cracow chip are presented.
In this paper we present a review of research results and technical accomplishments presented by researchers from technical universities, governmental institutes and research companies during the XIIth Scientific Conference Electron Technology, ELTE 2016. This review is based on materials presented at four topical conference sessions: Microelectronics and Nanoelectronics, Photonics, Materials and Technologies, and Microsystems and also on materials presented by invited speakers at two dedicated sessions. Oral sessions were accompanied by the poster sessions. In effect about 50 papers gathered in this volume reflect the topics discussed at the Conference. A short description of technological and measurement possibilities in the laboratories of Academic Centre for Materials and Nanotechnology and also in the Department of Electronics of the Faculty of Computer Science, Electronics and Telecommunications AGH UST are given.
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