The presented linear mode avalanche photodiode (APD) uses the standard layers and process steps available in the 0.35-μ m Si bulk CMOS process. Due to a low-doped epitaxial layer with a resistivity of 664 Ω cm , a deep intrinsic zone is realized to enable a large depleted absorption region at already moderate bias voltages and therefore ensures a high low-voltage responsivity. In combination with avalanche gain at high bias voltages, this leads to an overall responsivity of 1.7×10 5 A/W at 1.1 nW optical input power and 670-nm wavelength. The maximum achieved avalanche gain was 4.94×10 5 . The maximum −3 dB frequency of 700 MHz was measured at a reverse bias voltage of 30 V and an optical input power of 14.7 μ W.
Within this work a single pixel Time-of-Flight (TOF) based range finder is presented. The sensor is fabricated in a 0.35 μm 1P4M CMOS process occupying an area of 45 × 60 μm2 at ~50% fill factor. It takes advantage of the integrated PIN photodiode, representing, to the best knowledge of the author, the first reported TOF device done in this technology with a PIN detector. The measurement results show a standard deviation of 1 cm for a total integration time of 2.2 ms and a received optical power of 10 nW. Furthermore, the maximal measured integration time per single phase step is slightly below 1 ms, being an improvement by the factor of 40 over the previous work using a similar approach. As proven with the measurements, the background light influence on the measured distance can be neglected even if the dc light is by the factor of 600 larger than the modulation signal.
The presented paper describes a 10 Gbps optical receiver. The transimpedance amplifier (TIA) is realized in standard
0.35 μm SiGe BiCMOS technology. The main novelty of the presented design - investigated in the European
Community project HELIOS - is the hybrid connection of the optical detector. The used Germanium photodetector will
be directly mounted onto the receiver.
A model of the relevant parasitics of the photodetector itself and the novel connection elements (micropads, metal vias
and metal lines) is described. Based on this photodetector model an optical receiver circuit was optimized for maximum
sensitivity at data rates in the range of 10 Gbps.
The design combines a TIA and two limiting amplifier stages followed by a 50 Ω CML-style logic-level output driver.
To minimize power supply noise and substrate noise, a fully differential design is used. A dummy TIA provides a
symmetrical input signal reference and a control loop is used to compensate the offset levels. The TIA is built around a
common-emitter stage and features a feedback resistor of 4.2 Ω. The total transimpedance of the complete receiver
chain is in the range of 275 kΩ. The value of the active feedback resistor can be reduced via an external control voltage
to adapt the design to different overall gain requirements. The two limiting amplifier stages are realized as differential
amplifiers with voltage followers. The output buffer is implemented with cascode differential amplifiers. The output
buffer is capable of driving a differential 50Ω output with a calculated output swing of 800mVp-p.
Simulations show an overall bandwidth of 7.2 GHz. The lower cutoff frequency is below 60 kHz. The equivalent input
noise current is 408 nA. With an estimated total photodiode responsivity of 0.5 A/W this allows a sensitivity of around -
23.1 dBm (BER = 10-9). The device operates from a single 3.3 V power supply and the TIAs and the limiting amplifier
consume 32 mA.
We report on monolithically integrated PIN photodiodes whose responsivity values could be significantly enhanced over
the whole spectral range by the implementation of a Bottom Antireflective Coating (BARC) process module into
austriamicrosystems 0.35μm CMOS as well as high-speed SiGe BiCMOS technologies. The resulting photodiodes
achieve excellent responsivities together with low capacitances and high bandwidths. We processed finger-photodiodes
with interdigitated n+ cathodes, which are especially sensitive at low wavelengths, and photodiodes with full area n+
cathodes on very lightly p-doped start material. We present a method of depositing an antireflective layer directly upon
the Si surface of the photodiode by changing the standard process flow as little as possible. With just one additional mask
alignment and a well controlled etch procedure we manage to remove the thick intermetal oxide and passivation nitride
stack over the photodiodes completely without damaging the Si surface. The following deposition of a CVD Silicon
Nitride BARC layer not only minimizes the reflected fraction of the optical power but also acts as passivation layer for
the photodiodes. Another benefit of BARC processing is the fact that in-wafer and wafer-to-wafer quantum efficiency
variations can be dramatically reduced. In our experiments we deposited BARC layers of different thicknesses that were
optimised for violet, red and infrared light. Responsivity measurements resulted in values as high as R=0.27A/W at
λ=410nm, R=0.53A/W at λ=670nm and R=0.5A/W at λ=840nm.
Herein we present optical receivers with external large-area photodiode. It is intended as POF receiver for 1.25Gb/s optical fiber-line access networks. Further an overview on high-speed optical receivers with integrated and external detector in CMOS and BiCMOS, as well as in technologies of III-V compounds is provided. This work's receiver circuits are realized in 0.35μm SiGe BiCMOS technology. The first amplifier stage is a two-transistor transimpedance amplifier using a common-emitter and an emitter-follower configuration. The light-sensitive areas of the two receivers presented are 0.25mm2 (squared PIN diode) and 0.5mm2 (circular APD), with a rise time of 0.4ns and 0.7ns, respectively, at 850nm light. A high sensitivity is also required, where the receiver with external PIN diode reaches a sensitivity of -25.9dBm at the optical input using low-cost silicon-based material only.