One of the key methods targeted for continuing the resolution scaling in new device technology nodes is the trend towards using curvilinear mask patterns. With recent advances in multi-beam mask patterning and large-scale adoption of ILT mask data correction, curvilinear (and all-angle) mask patterns are considered today as a mainstream technology option. Curvilinear mask patterns provide improved wafer resolution and OPC/ILT mask correction control with reduced mask manufacturing issues related to tight corners and line-ends. However, OPC, ILT, LRC and other full-chip simulation-based mask synthesis methods also require more accurate electromagnetic (i.e., M3D) simulation for new technology nodes. Prior full-chip electromagnetic simulation methods have often assumed that mask patterns are restricted to Manhattan geometries or utilize limited angles. Therefore, there is a general industry need for improved electromagnetic full-chip simulation methods for curvilinear mask patterns. This paper will present a new electromagnetic full-chip simulation method for curvilinear mask patterns that will improve the accuracy of mask synthesis methods at upcoming technology nodes. This method can provide both accuracy and speed benefits on mask synthesis with curvilinear mask patterns for both DUV and EUV lithography. The method utilizes an enhanced physics-based treatment of electromagnetic mask scattering both tuned and verified by rigorous electromagnetic Maxwell’s equation solvers.
In this paper we will evaluate the impact of stitching on process window and show how EDA can help to improve the manufacturability of stitched layers. More specifically, we demonstrate modeling of double exposure effects suitable for full-field correction and verification that incorporates aerial image cross-talk, optical black border transitions, subresolution gratings, sub-resolution assist-features and long-range flare. We also evaluate how stitching impacts different high NA processes and how correction of these effects (ex. via optical proximity correction, inverse lithography technology) can be used to increase process robustness. Finally, we examine the impact of stitched pattern overlap to process window and how loss of process window due to stitching can be mitigated.
EUV lithography has been ramped to successful volume manufacturing through a combination of improvements in process technology, layout design and device interactions, and also optimization of the overall product integration to reduce undesirable interactions. Because EUV has additional sources of systematic and stochastic variation that did not exist in DUV lithography, it is now even more important to have accurate predictive capability to test and understand the design and lithography process interactions. EUV-specific physical behavior such as shadowing, flare, mask topography (i.e., Mask3D) effects, mask stack reflectivity, mask absorber behavior and other effects are key differences in how EUV forms an image on the mask and subsequently on the wafer. The reflective mask substrate and EUV-specific mask absorber stack are therefore highly important technologies to optimize as the industry pushes both low NA (0.33NA) and high NA (0.55NA) technologies to cover the patterning requirements of upcoming 3nm and below technology nodes. Recently there have been substantial industry interest in optimizing EUV mask stacks to further enhance imaging behavior and achieve better pattern resolution, increase process window, lower stochastic defectivity and optimize flare. Several different options have been proposed for these new EUV mask stacks for lower K1 EUV patterning. All of these new options require excellent simulation accuracy in OPC, SrAF placement, OPC verification and ILT mask synthesis steps in order to realize the benefits of the new mask stacks. In this paper we will focus on analyzing and improving the accurate prediction of a range of new EUV mask stack options for full-chip OPC/ILT compatible compact models. We will show for advanced mask designs the accuracy requirements and capability of leading-edge compact models. The accuracy requirements and capability will be referenced to fully rigorous electromagnetic solver (e.g., Mask3D) results to ensure industry needs are met. We will also explore the mask stack options to highlight the imaging benefits for different material thickness, refractive index (n) and extinction coefficient (k) on important mask pattern feature and layer types.
The first high-NA EUVL scanner will have an 0.55 NA and will use anamorphic magnification. Therefore, the standard 10×13 cm lithography mask will be imaged into a 2.6×1.65 cm rectangle on the wafer due to the increased reduction factor of the lens’ vertical direction. Layers exposed on high-NA anamorphic scanners will require two stitched halffields to achieve the equivalent exposure area of previous-generation scanners. Stitching strategies will depend on the product type being manufactured. For chips with a large die area, it will be necessary to stitch fields across the die. For smaller chips, it may be advantageous to use three stitched exposures depending on the die size. In any case, the stray light from neighboring fields and black border proximity effects cause challenges for robust manufacturing. Some recent studies have shown that the CD may vary significantly as a function of the proximity to the black border edge due to multilayer stresses. In addition, stitching through a die has increased optical proximity effects which will need to be corrected to achieve the desired wafer CD. In this paper we examine the effects relevant to designing a stitched process, quantify manufacturing tolerances, and show how these effects can be corrected with EDA. More specifically, we examine the optical and mechanical properties of the multi-layer black border etch and optimization of sub-resolution gratings to reduce reflectivity with phase shifting absorber materials. Ultimately, we will show that for a well designed stitch, the effects of stitching can be corrected without impact to process window.
Integrated circuit performance has been limited by transistor performance for many process nodes. However, in advanced nodes where pitches reach 10s of nanometers in size, there is an increasing probability of cases where circuit timing may be limited by the resistance and capacitance of the device rather than the transistor. This means that metal layer patterning may have implications on device performance beyond reliability, shorts, and opens. Lithography variation can be effectively predicted using stochastic simulations, including layer overlay. Simulating many patterns stochastically produces insight into the performance of the lithography process over time. Etching and metallizing the pattern set in simulation then allows the study to extend to electrical simulations. The combined lithography and electrical simulation data can then be used together to improve process or pattern performance before constructing a reticle. These data also allow the engineering teams to address resist and capacitance issues that may impact device performance prior to tapeout. This paper will investigate the metal layers of a structure designed to emulate an advanced node logic circuit that uses a CFET transistor. The structure will be corrected with OPC, and each layer will be simulated to generate a large (100) set of stochastic patterns at multiple process conditions in focus, overlay, and exposure. Each of these patterns will then be etched in a modeled process and metalized with copper. Finally, resistance and capacitance measurements will be generated from circuit simulations. The output data will then be used to update the lithography process or the pattern to improve through process performance including electrical characteristics.
KEYWORDS: Calibration, Data modeling, Resolution enhancement technologies, Process modeling, Scanning electron microscopy, Data acquisition, Optical lithography, Metrology, Lithography, Computer simulations
Computational lithography applications for OPC/ RET utilize models that represent the lithographic process in simulations. The quality of OPC/ RET wafer results strongly depends on the quality of the model. Hence, achieving model quality and experimental match is the goal of the model calibration process where models are calibrated to experimental data. Ideally, the model would be calibrated and validated to a data set that completely covers the entire design space and all process conditions. A promising alternative to the traditionally applied SEM-CD-based model calibration is the calibration to pattern contours directly with benefits in design space coverage, reduced metrology effort and data preparation complexity. However, contour calibration also demands a new standard operating procedure for contour specific metrology, pattern design and calibration. Goal of this work is to develop and exercise a full contour-based calibration methodology. Firstly, we discuss preconditions for a successful calibration: good quality contour input data, predictive modeling of optics, mask topography and 3D resist and additional calibrator functionality to include aspects of alignment and pattern specific measurement confidence. Secondly, we assess pattern for their calibration-suitability using a metric for pattern information density. Experiments are performed to show the applicability of the metric and the potential to calibrate to a minimal set of patterns. A model calibrated to a well selected single 2.25 μm2 contour is predicting a large set of pattern contours, 3D resist characteristics and SEM-CD focus-exposure process windows.
The consideration of wafer topography effects in lithographic modeling of implant layers is mandatory for sub 32nm processes. The approximate assumption that both oxide- and resist thickness are independent of pattern design can lead to large model prediction errors and OPC correction failure. An implant lithography modeling flow based on rigorous models is presented that covers a) the STI stack formation and its etch–proximity effects, b) the resist spin-on and resulting thickness fluctuations, c) the image formation in the modeled stack and d) the chemical characterization of implant photoresist. This approach shows accuracy benefits and will be used to augment the existing OPC correction flow.
The difficulties involved in ramping EUV lithography to volume manufacturing have highlighted the critical task of understanding process, layout design and device interactions, and also of optimizing the overall product integration to reduce undesirable interactions. In this paper, we demonstrate mask synthesis methods that using rigorous EUV lithography models together with inverse lithography technology (ILT) for EUV process window and CD control improvement. To enable this new capability, we have linked the broad EUV physical effect modeling capability of our rigorous lithography simulator, Sentaurus Lithography (S-Litho), with our highly flexible production proven ILT mask synthesis solution (Proteus ILT). This new combined capability can take advantage of the wide range of EUV modeling capabilities including rigorous electromagnetic mask/substrate modeling. The advantages of using S-Litho rigorous simulation for ILT optimization is further benefited from significant speed enhancements using new high performance EUV mask 3D capabilities. ILT has been extensively used in a range of lithographic areas for DUV and EUV including logic hot-spot fixing, memory layout correction, dense memory cell optimization, assist feature (AF) optimization, source optimization, complex patterning design rules and design-technology co-optimization (DTCO). The combined optimization capability of these two technologies therefore will have a wide range of useful EUV applications. We will highlight the specific benefits of the rigorous DUV and EUV ILT functionality for several advanced applications including resist profile optimization for resist top- oss and resist descumming and process window improvement.
As EUV lithography is getting ready for deployment in high volume manufacturing, lithography engineering focus moves to efficient computational lithography tools (mask correction, verification, source-, mask- and processoptimization) providing optimal RET solutions for EUV early design exploration. Key to computational lithography success is the prediction ability of the underlying lithography process simulation model. Topographic mask effects prediction is one of the major challenges with significant impact on both simulation quality of results and turn around time. In this paper, we apply a fast modeling approach to EUV light diffraction on topographic masks, which is based on fully rigorous topographic mask simulations. It is demonstrating performance benefits of several orders of magnitude while maintaining the accuracy requirements for productive cases. We explore its applicability to medium sized computational lithography tasks. The accurate mask solver results will be complemented with imaging and 3D resist simulations using the rigorous lithography simulator S-Litho by Synopsys.
Despite the large difficulties involved in extending 193i multiple patterning and the slow ramp of EUV lithography to full manufacturing readiness, the pace of development for new technology node variations has been accelerating. Multiple new variations of new and existing technology nodes have been introduced for a range of device applications; each variation with at least a few new process integration methods, layout constructs and/or design rules. This had led to a strong increase in the demand for predictive technology tools which can be used to quickly guide important patterning and design co-optimization decisions.
In this paper, we introduce a novel hybrid predictive patterning method combining two patterning technologies which have each individually been widely used for process tuning, mask correction and process-design cooptimization. These technologies are rigorous lithography simulation and inverse lithography technology (ILT). Rigorous lithography simulation has been extensively used for process development/tuning, lithography tool user setup, photoresist hot-spot detection, photoresist-etch interaction analysis, lithography-TCAD interactions/sensitivities, source optimization and basic lithography design rule exploration. ILT has been extensively used in a range of lithographic areas including logic hot-spot fixing, memory layout correction, dense memory cell optimization, assist feature (AF) optimization, source optimization, complex patterning design rules and design-technology co-optimization (DTCO). The combined optimization capability of these two technologies will therefore have a wide range of useful applications. We investigate the benefits of the new functionality for a few of these advanced applications including correction for photoresist top loss and resist scumming hotspots.
As minimum feature size shrinks to a metal pitch of 21 nm, the current extreme ultra violet (EUV) lithographic tool with a numeric aperture (NA) of 0.33 will face resolution limit for some critical layers. High NA (0.55) EUV with anamorphic optics or EUV double patterning (DP) at 0.33 NA are being considered for the next generation of lithographic technology. Both the high NA EUV system and EUV DP will enhance resolution relative to current EUV single patterning (SP). Nevertheless, in order to be able to compare EUV DP and High NA EUV processes, important lithographic factors including image contrast, mask three dimension (M3D) effects, process variation band, stochastic effects and local critical dimension uniformity need to be investigated to understand their contributions to process variations. This study was carried out using rigorous lithographic model simulations in Sentaurus Lithography, where strong M3D effects in EUVL are computed physically. We have simulated patterns with both isomorphic and anamorphic optical proximity corrections (OPC) using the rigorous model. The study focuses on 3nm node Via layer designs. These vias need to connect to metal features which have pitches of 21 nm. Simulation results using 0.33 NA SP, 0.33 NA DP, and 0.55 NA anamorphic SP are presented. The benefit of using an alternative mask absorber and a thinner resist as well as the impact of stochastic effects have also been explored. Although a 0.55 NA EUV is expected to produce a superior image to 0.33 NA EUV and to have less impact from overlay errors and stochastic effects, an analysis of process margins of 0.33 NA EUV SD and DP versus 0.55 NA anamorphic systems helps to better understand the benefits, challenges and optimal insertion point for introducing High-NA EUV.
New inverse methods such as model-based SRAF placement, model-based SRAF optimization, and full main + assist
feature ILT are well known to have considerable benefits in finding flexible mask pattern solutions to improve process
window and CD control. These methods have traditionally relied on compact models that are tuned to match resist
measurements at a single z-height or slice. At this slice in the resist, some critical failure modes such as top loss and
scumming are not detected. In this paper, we describe and present results for a methodology to extend ILT’s process
window improvement capabilities, and to co-optimize mask patterns with awareness of the resist profile. These
improvements are proven to reduce the risk of patterning failures at the bottom and top of critical resist features, which a
typical mask correction process would not alleviate. Ideally, mask optimization would use a full rigorous TCAD resist
model to guide the correction at multiple heights in the resist. However, TCAD models are significantly slower than
compact models in simulations and ILT already has high computational requirements. Therefore, we have generated
compact models which are fitted to the TCAD model resist profile data. We show the significant process window
improvements obtained with this new resist 3D aware ILT methodology.
While critical lithographic feature size diminishes, resist profile can vary significantly as image varies. As a consequence, the final etch results are becoming more dependent on 3D resist profile rather than only a simple 2D resist image as an etch mask. Therefore, it has become necessary to build resist profile information into OPC models, which traditionally only contain 2D information in the x-y plane. At the same time, rigorous lithographic simulators are capable of modeling 3D resist profiles on a small chip area. In this work, one approach is investigated to account for 3D resist profile characteristics in full-chip OPC models with the assistance of rigorous simulation. With measurement data collected from experimental wafers, a rigorous resist model is first calibrated and verified. Then individual compact models are built to match the rigorous resist model profile at specified resist heights. The calibrated compact model for bottom resist line width corresponds to a conventional OPC model while resist profile is described by multiple models specified for certain resist heights, with each model being in the form of conventional compact models. In practice, the bottom model along with one or two models at critical heights are usually sufficient to detect sites where etch results become sensitive to resist profile. It has been found that the rigorous resist profile model can be well matched by the suggested compact models. For a quick application demonstration, hot spots of the etch results in the test case have been shown to be successfully captured by the calibrated compact models.
KEYWORDS: Calibration, Monte Carlo methods, Photoresist processing, Electron beam lithography, Data modeling, Process modeling, Scanning electron microscopy, Computer simulations, Scattering, Chemically amplified resists
With the constantly improving maturity of e-beam direct write exposure tools and processes for applications in high volume
manufacturing, new challenges with regard to speed, throughput, correction and verification have to be faced. One objective
of the MAGIC high-throughput maskless lithography project [1] is the application of the physics-based simulation in a
virtual e-beam direct write environment to investigate proximity effects and develop comprehensive correction
methodologies [2]. To support this, a rigorous e-beam lithography simulator for the feature scale has been developed [3]. The
patterning behavior is determined by modeling electron scattering, exposure, and resist processing inside the film stack, in
analogy with corresponding simulation capabilities for the optical and EUV case. Some model parameters, in particular for
the resist modeling cannot be derived from first principles or direct measurements but need to be determined through a
calibration process.
To gain experience with the calibration of chemically amplified resists (CAR) for e-beam lithography, test pattern exposures
have been performed for a negative tone CAR using a variable-shaped beam writer operating at 50kV. A recently
implemented model calibration methodology has been applied to determine the optimum set of resist model parameters.
While the calibration is based on 1D (lines & spaces) patterns only, the model results are compared to 2D test structures for
verification.
KEYWORDS: Data modeling, 3D modeling, Electron beam direct write lithography, Point spread functions, Critical dimension metrology, Model-based design, Geometrical optics, Cadmium, Error analysis, Virtual reality
We demonstrate a flow for e-beam proximity correction (EBPC) to e-beam direct write (EBDW) wafer manufacturing
processes, demonstrating a solution that covers all steps from the generation of a test pattern for (experimental or virtual)
measurement data creation, over e-beam model fitting, proximity effect correction (PEC), and verification of the results.
We base our approach on a predictive, physical e-beam simulation tool, with the possibility to complement this with
experimental data, and the goal of preparing the EBPC methods for the advent of high-volume EBDW tools.
As an example, we apply and compare dose correction and geometric correction for low and high electron energies on
1D and 2D test patterns. In particular, we show some results of model-based geometric correction as it is typical for the
optical case, but enhanced for the particularities of e-beam technology.
The results are used to discuss PEC strategies, with respect to short and long range effects.
For advanced technology nodes, a large amount of effort must be spent to optimize area critical full-custom layouts with respect to their manufacturability. Due to the strong irregularity and two-dimensionality of these layouts, it appears impossible to fully capture the corresponding complex requirements with design rules in order to be able to perform a rule-based physical verification in form of a "design rule check" (DRC). Alternative approaches have to be found and one of them is presented in this paper. The complexity of the DRC can be significantly reduced for rules focused on process aspects. Those rules can be replaced by a "simulation rule check" (SRC), where at first process simulations (like e.g. lithography) are done and then a set of straightforward rules is applied to geometrical entities representing the simulation output instead of the layout geometry. Thus, this new set of rules works more directly on the core of the matter. The "litho-friendly design environment" (LFD) provided by Mentor Graphics offers the tools for this approach. The SRC includes intra-layer checks like area, width, and space checks as well as interlayer checks, such as overlap. To the physical designer, SRC violations are presented in a DRC like fashion, including error scoring and classification. This paper will demonstrate the application of LFD and highlight the usability of this infrastructure for layout optimization using an SRC for physical verification.
For the technology development of microlithography various optical simulation tools are established as a planning and development tool. Depending on the application, various numerical approximation schemes are used to tradeoff accuracy versus speed. Determining the correct numerical setting is often a tricky task as it is a compromise between these two contrary properties. In our study, we compare the numerical accuracy of two optical simulators, Solid-E as a representative for simulators for technology development and Mentor Calibre as design-for-manufacturing and optical proximity correction (OPC) tool. Calibre uses a coherent kernel approximation for performing fast simulations. As a measure for the simulation accuracy, we use the root-mean-square error criterion of a linearity curve compared to an analytical reference simulation.
As in optical lithography, E-beam lithography is facing a multitude of issues, both in mask making and in direct write applications. These issues range from pattern printability and design verifications to tool and process optimizations. Simulation can be used to address these issues, however its applicability was limited due to limitations in the usable simulation area. Advances in the mathematical models lead to a significant speedup of the simulation, enabling the simulation of larger areas. This paper will demonstrate the applicability of the new simulator on a few key examples, such as aggressive mask challenges, model to experiment correlations as well as its application to direct write.
In this paper we examine new models and the indispensability of model parameters of chemically amplified resists (CAR) for their usage in predictive process simulation. Based on a careful exploration of different modeling options we calibrate the model parameters with different experimental data. Furthermore, we investigate different modeling approaches: (1) Mode of coupling between diffusion and kinetic reactions, sequence of quencher base events (Hinsberg model); (2) Mode of diffusion: Fickian and linear diffusion model; (3) Development rate model: Performance of the Enhanced Notch model. The resulting models are evaluated with respect to their performance by comparing with experimental line-width for semidense (1-2, 1-1.6, 1-1.4, 1-1.2) and dense features, the bias between different features and full resist profiles. The investigations are applied to the Shipley resist UVTM 113. Finally, a parameter extraction procedure for chemically amplified resists is proposed.
KEYWORDS: Lithography, Standards development, Data modeling, Promethium, Photoresist materials, Photoresist processing, Diffusion, Inspection, Process modeling, Picture Archiving and Communication System
The use of experimental development rate information is used to demonstrate various deficiencies in the dissolution rate equations commonly employed in commercial lithography simulation programs. An improved version of the Notch dissolution rate equation, incorporating one new parameter, is proposed, which addresses the observed deficiencies. Simulation work comparing the new equation to the standard Notch model reveals significant differences in process window and exposure margin, yet negligible changes in feature profile and iso-dense bias at best focus and exposure.
Lithography simulators have become a standard tool in industrial and governmental research and development departments. IN contrast to the modeling approaches for the optical system and for the lithographic performance of i- line resists, there is still no consensus on the modeling of chemically amplified resist (CAR). Existing models differ in the description of the kinetics and the diffusion phenomena during post exposure bake and in the specification of the development rate. A modeling approach was established, that combines the light induced generation of photoacid, in- and out-diffusion of acid or base components, a generalized deprotection kinetics, Fickian and non-Fickian diffusion of resist components and an arbitrary development rate model. Existing models such as the effective acid model and a standard deprotection model for CAR can be considered as special cases of the implemented model. To evaluate the importance of certain options of the model and of the model parameters we have evaluated the performance of the model by comparing simulated CD data and resists profiles with experimental data.
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