Deep learning has recently been successfully applied to lithography hotspot detection. However, automatic correction of the detected hotspots into non-hotspots has not been explored. This problem is challenging because the standard supervised learning requires a training dataset with pairs of hotspots and non-hotspots, which is impractical to collect because lithography hotspots involve diverse and complicated lithographic pattern properties. In this paper, we propose a new framework for lithography hotspot correction with a deep generative network combined with a learning strategy optimized for lithography patterns. Our key idea is to learn to translate hotspots to non-hotspots and vice versa, simultaneously. In this way, the training dataset does not have to be paired, and hotspot patterns in variety of background can be learned. Our method does not require the understanding of the cause of hotspots and can correct hotspots that are difficult to recognize by conventional approaches. For evaluation, we propose to synthesize a training dataset that reflects a variety of real-world lithography patterns. Experimental results show that our framework can correct hotspot images with comparable quality as a conventional complicated process, while significantly reducing the overall processing time.
It is well known in the industry that the technology nodes from 30nm and below will require model based SRAF / OPC
for critical layers to meet production required process windows. Since the seminal paper by Saleh and Sayegh
thirty years ago, the idea of using inverse methods to solve mask layout problems has been receiving increasing attention
as design sizes have been steadily shrinking. ILT in its present form represents an attempt to construct the inverse
solution to a constrained problem where the constraints are all possible phenomena which can be simulated, including:
DOF, sidelobes, MRC, MEEF, EL, shot-count, and other effects. Given current manufacturing constraints and process
window requirements, inverse solutions must use all possible degrees of freedom to synthesize a mask.
Various forms of inverse solutions differ greatly with respect to lithographic performance and mask complexity. Factors
responsible for their differences include composition of the cost function that is minimized, constraints applied during
optimization to ensure MRC compliance and limit complexity, and the data structure used to represent mask patterns. In
this paper we describe the level set method to represent mask patterns, which allows the necessary degrees of freedom
for required lithographic performance, and show how to derive Manhattan mask patterns from it, which can be
manufactured with controllable complexity and limited shot-counts. We will demonstrate how full chip ILT masks can
control e-beam write-time to the level comparable to traditional OPC masks, providing a solution with maximized
lithographic performance and manageable cost of ownership that is vital to sub-30nm node IC manufacturing.
For low k1 lithography the resolution of critical patterns on large designs can require advanced resolution enhancement
techniques for masks including scattering bars, complicated mask edge segmentation and placement, etc. Often only a
portion of a large layout will need this sophisticated mask design (the hotspot), with the remainder of layout being
relatively simple for OPC methods to correct. In this paper we show how inverse lithography technology (ILT) can be
used to correct selected regions of a large design after standard OPC has been used to correct the simple portions of the
The hotspot approach allows a computationally intensive ILT to be used in a limited way to correct the most difficult
portions of a design. We will discuss the most important issues such as: model matching between ILT and OPC
corrections; transition region corrections near the ILT and OPC boundary region; mask complexity; total combined
runtime. We will show both simulated and actual wafer lithographic improvements in the hotspot regions.
For semiconductor IC manufacturing at sub-30nm and beyond, aggressive SRAFs are necessary to ensure sufficient
process window and yield. Models used for full chip Inverse Lithography Technology (ILT) or OPC with aggressive
SRAFs must predict both CDs and sidelobes accurately. Empirical models are traditionally designed to fit SEMmeasured
CDs, but may not extrapolate accurately enough for patterns not included in their calibration. This is
particularly important when using aggressive SRAFs, because adjusting an empirical parameter to improve fit to CDSEM
measurements of calibration patterns may worsen the model's ability to predict sidelobes reliably. Proper choice of
the physical phenomena to include in the model can improve its ability to predict sidelobes as well as CDs of critical
patterns on real design layouts. In the work presented here, we examine the effects of modeling certain chemical
processes in resist. We compare how a model used for ILT fits SEM CD measurements and predicts sidelobes for
patterns with aggressive SRAFs, with and without these physically-based modeling features. In addition to statistics
from fits to the calibration data, the comparison includes hot-spot checks performed with independent OPC verification
software, and SEM measurements of on-chip CD variation using masks created with ILT.