Extreme ultraviolet lithography (EUVL) systems struggle from both low source brightness and low source throughput through the tool. For these reasons, photon shot noise will play a much larger role in image process development for EUVL than in DUV processes. Furthermore, the lower photon count increases the stochastic variation of all the processes which occur after photon absorption. This causes the printed edge to move away from the mean edge with some probability. This paper will present a model form and calibration flow for including stochastic probability bands in compact models suitable for full chip simulation. This model form relies on calibrating to statistical data from a rigorous EUV stochastic lithography model calibrated to wafer experimental data. The data generation, data preparation, and model calibration flows for the compact stochastic probability bands will be presented. We will show that this model form can predict patterns which are prone to stochastic pattern failure in realistic mask designs, as well as how this model form can be used downstream for full chip correction (e.g., SMO, OPC and/or ILT).
With the delay in commercialization of EUV and the abandonment of high index immersion, Fabs are
trying to put half nodes into production by pushing the k1 factor of the existing scanner tool base as
low as possible. A main technique for lowering lithographic k1 factor is by moving to very strong offaxis
illumination (i.e., illumination with high outer sigma and a narrow range of illumination angles),
such as Quadrapole (e.g., C-Quad), custom or even dipole illumination schemes. OPC has generally
succeeded to date with rule-based techniques for dissecting edges into segments and placing target
points. Very strong off-axis illumination, however, creates pronounced ringing effects on 2D layout
and this makes these simpler dissection techniques problematic. In particular, it is hard to prevent
overshoot of the contour around corners while simultaneously dampening out the ringing further
down the feature length. In principle, a sufficiently complex set of rules could be defined to solve this
issue, but in practice this starts to become un-manageable as the time needed to generate a usable
recipe becomes too long. Previous implementations of inverse lithography demonstrated that good
CD control is possible, but at the expense of the mask costs and other mask synthesis
complications/limitations. This paper first analyzes the phenomenon of ringing and the limitations
seen with existing simpler target placement techniques. Then, different methods of compensation are
discussed. Finally, some encouraging results are shown with some model based techniques that the
authors have investigated, some of which only demand incremental changes to the existing OPC
framework. The results show that new OPC techniques can be used to enable successful use of very
strong off-axis illumination conditions in many cases, to further reduce lithographic k1 limits.
Model based optical proximity correction (MB-OPC) has been widely used in advanced lithography process today.
However controlling the edge placement error (EPE) and critical dimension (CD) has become harder as the k1 process
factor decreases and design complexity increases. Especially, for high-NA lithography using strong off-axis
illumination (OAI), ringing effects on 2D layout makes CD control difficult. In addition, mask rule check (MRC) limits
also prevent good OPC convergence where two segment edges are corrected towards each other to form a correction-conflicting
scenario because traditional OPC only consider the impact of the current edge when calculating the edge
movement. A more sophisticated OPC algorithm that considers the interaction between segments is necessary to find a
solution that is both MRC and convergence compliant.
This paper first analyzes the phenomenon of MRC-constrained OPC. Then two multiple segment correction techniques
for tolerance-based OPC and MRC-constrained OPC are discussed. These correction techniques can be applied to
selected areas with different lithographic specifications. The feasibility of these techniques is demonstrated by
quantifying the EPE convergence through iterations and by comparing the simulated contour results.
The steady march of Moore's law demands ever smaller feature sizes to be printed and
Optical Proximity Correction to correct to ever tighter dimensional tolerances. Recently
pitch doubling techniques has relieved the pressure on CD reduction, which instead of
being achieved lithographically are reduced by subsequent etching or chemical
interaction with spin-on layers. CD tolerance reductions, however, still need to match the
overall design rule shrinkage. The move to immersion lithography, where effective
Numerical Apertures now reach 1.35, has been accompanied by a significantly reduction
in depth of focus, especially on isolated contacts. To remedy this, RET techniques such
as assist feature placement, have been implemented. Certain local placements of assist
features and neighboring contacts are observed to result in highly elliptical contacts being
printed. In some layouts small changes in the aspect ratio of the contact on the mask leads
to strong changes in the aspect ratio of the printed contact, whereas in other layouts the
response is very weak. This effect can be described as an aspect ratio MEEF. The latter
type of contact can pose a significant challenge to the OPC recipe which is driven by the
need to place the printed contour within a small range of distance from target points
placed on the midpoint of edges of a nominally square contact. The OPC challenge
naturally will be compounded when the target layout is rectangular in the opposite sense
to the natural elliptical shape of the printed contact. Approaches to solving this can vary
from intervening at the assist feature placement stage, at the possible loss of depth of
focus, to accepting a certain degree of ellipticity in the final contour and making the OPC
recipe concentrate on minimizing any residual errors. This paper investigates which
contact layouts are most challenging, discusses the compromises associated with
achieving the correction target and results are shown from a few different approaches to
resolving these issues.
In this paper, we present some important improvements on our process window aware OPC (PWA-OPC). First, a CDbased
process window checking is developed to find all pinching and bridging errors; Secondly, a rank ordering method
is constructed to do process window correction; Finally, PWA-OPC can be applied to selected areas with different
specifications for different feature types. In addition, the improved PWA-OPC recipe is constructed as sequence of
independent modules, so it is easy for users to modify its algorithm and build original IPs.
A variety of innovations including the reduction of actinic wavelength, an increase in lens NA, an
introduction of immersion process, and an aggressive OPC/RET technique have enabled device shrinkage
down to the current 45nm node. The immaturity of EUV and high index immersion, have made logic
manufacturers look at other ways of leveraging existing exposure technologies as they strive to develop
process technology for 32nm and below. For design rules for sub-nodes from 32nm to 22nm, the need to
define critical layers with double photolithography and etch process becomes increasingly evident.
Double patterning can come in a variety of forms or 'flavors'. For 32/28nm node, the patterning of 2D
features is so challenging that opposing line-ends can only be defined using an additional litho and etch
step to cut them. For 22nm node, even line/space gratings are below the theoretical k1=0.25 imaging limit.
Therefore pitch-doubling double patterning decomposition is absolutely required. Each double patterning
technology has its own set of challenges. Most of all, an existing design often cannot be shrunk blindly and
then successfully decomposed, so an additional set of restrictions is required to make layouts double
patterning compliant. To decompose a logic layout into two masks, polygons often need to be cut so that
they can be patterned using both masks. The electric performance of this cut circuitry may be highly
dependent on the quality of layout decomposition, the circuit characteristics and its sensitivity to
misalignment between the two patterning steps. We used representative logic layouts of metal level and
realistic models to demonstrate the issues involved and attempt to define formal rules to help enable lineend
splitting and pitch-doubling double patterning decomposition. This study used a variety of shrink
approaches to existing legacy layouts to evaluate double patterning compliance and a careful set-up of
parameters for the pitch splitting decomposition engine. The quality of the resultant imaging was tuned
using double patterning aware OPC and printability verification tools.
Double patterning technology (DPT) is one of the main options for printing critical layers at
32nm half-pitch and beyond. To enable DPT, a layout decomposition tool is first used to split the
original design into two separate decomposed-design layouts. Each decomposed-design layout
may then receive optical proximity correction (OPC) and RETs to produce a mask layout. The
requirements for OPC to enable individual layer DPT patterning are generally the same as
current single exposure OPC requirements, meaning that the success criteria will be similar to
previous node specifications. However, there are several new challenges for OPC with DPT.
These include large litho-etch biases, two sets of process variables associated with each
patterning layer and the relative pattern placement between them. The order of patterning may be
important as there may be process interactions between the two patterns especially at overlap
regions. Corners which were rounded in single patterning layers may now become sharp,
potentially increasing reliability concerns due to electromigration. In this study, we address many
of these issues by proposing several new techniques that can be used in OPC with DPT. They
are specifically designed for the Litho-Etch-Litho-Etch process, but some of the ideas may be
extended to develop OPC methods for other DPT processes. We applied the new OPC method to
several circuit and test patterns and demonstrated how OPC results were improved compared to
regular OPC methods.
Due to shrinking design nodes and to some limitations of scanners, extreme off-axis illumination (OAI) required and
its use and implementation of assist features (AF) to solve depth of focus (DOF) problems for isolated features and
specific pitch regions is essential. But unfortunately, the strong periodic character of OAI illumination makes AF's print
more easily. Present OPC flows generate AFs before OPC, which is also causes some AF printing problems. At present,
mask manufacturers must downsize AF's below 30nm to solve this problem. This is challenging and increases mask cost.
We report on an AF-fixer tool which is able to check AF printability and correct weak points with minimal cost in
terms of DOF after OPC. We have devised an effective algorithm that removes printing AF's. It can not only search for
the best non-printing AF condition to meet the DOF spec, but also reports uncorrectable spots, which could be marked as
design errors. To limit correction times and to maximize DOF in full-chip correction, a process window (PW) model and
incremental OPC method are applied. This AF fixer, which suggests optimum AF in only weak point region, solves AF
printing problems economically and accurately.