Dr. Xiaoxiao (Michelle) Zhang Profile

Dr. Xiaoxiao (Michelle) Zhang

at GLOBALFOUNDRIES Inc

SPIE Involvement:

Author

Publications (6)

Proceedings Article | 24 March 2016 Paper

Improving OCD time to solution using Signal Response Metrology

Fang Fang, Xiaoxiao Zhang, Alok Vaid, Stilian Pandev, Dimitry Sanko, Vidya Ramanathan, Kartik Venkataraman, Ronny Haupt

Proceedings Volume 9778, 977806 (2016) https://doi.org/10.1117/12.2219775

KEYWORDS: Metrology, Optical metrology, Critical dimension metrology, Measurement devices, Time metrology, Lithography, Etching, Semiconducting wafers, Instrument modeling, Transistors, Model-based design, Signal processing, Scatterometry, Scanners, Data modeling, Control systems

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Proceedings Article | 18 March 2016 Paper

Device level 3D characterization using PeakForce AFM

Padraig Timoney, Xiaoxiao Zhang, Alok Vaid, Sean Hand, Jason Osborne, Eric Milligan, Adam Feinstein

Proceedings Volume 9778, 97781A (2016) https://doi.org/10.1117/12.2220152

KEYWORDS: Atomic force microscopy, Semiconducting wafers, 3D metrology, Transmission electron microscopy, Metrology, Pulmonary function tests, Metals, Scatterometry, Diffractive optical elements, Overlay metrology

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Traditional metrology solutions face a range of challenges at the 1X node such as three dimensional (3D) measurement capabilities, shrinking overlay and critical dimension (CD) error budgets driven by multi-patterning and via in trench CD measurements. With advent of advanced technology nodes and 3D processing, an increasing need is emerging for in-die metrology including across-structure and structure-to-structure characterization. A myriad of work has emerged in the past few years intending to address these challenges from various aspects; in-die OCD with reduced spot size and tilt beam on traditional critical dimension scanning electron microscopy (CDSEM) for height measurements. This paper explores the latest capability offered by PeakForce^TM Tapping Atomic Force Microscopy (PFT-AFM). The use of traditional harmonic tapping mode for scanning high aspect ratio, and complex “3D” wafer structures, results in limited depth probing capability as well as excessive tip wear. These limitations arise due to the large tip-sample interaction volume in such confined spaces. PeakForce Tapping eliminates these limitations through direct real time control of the tip-sample interaction contact force. The ability of PeakForce to measure, and respond directly to tip- sample interaction forces results in more detailed feature resolution, reduced tip wear, and improved depth capability. In this work, the PFT-AFM tool was applied for multiple applications, including the 14nm fin and replacement metal gate (RMG) applications outlined below. Results from DOE wafers, detailed measurement precision studies and correlation to reference metrology are presented for validation of this methodology. With the fin application, precision of 0.3nm is demonstrated by measuring 5 dies with 10 consecutive runs. Capability to resolve within-die and localized within-macro height variation is also demonstrated. Results obtained from the fin measurements support the increasing trend that measurements in the scribe line may not accurately represent in-die geometry, thus indicating the increasing need to measure the real device area. In-die measurement capability of peak force tapping AFM on wafers at post-poly-removal step in the RMG module is also evaluated. Precision of 1.22nm for the fin height under the gate, 1.06nm for the total gate height, and 0.77nm for the overburden are achieved in this application on a semidense structure. To the knowledge of the authors, this is the first demonstration of a robust in-die measurement of the fin height under the gate.

Proceedings Article | 15 March 2016 Paper

Line edge roughness frequency analysis for SAQP process

Lei Sun, Xiaoxiao Zhang, Shimon Levi, Adam Ge, Hua Zhou, Wenhui Wang, Navaneetha Krishnan, Yulu Chen, Erik Verduijn, Ryoung-han Kim

Proceedings Volume 9780, 97801S (2016) https://doi.org/10.1117/12.2229176

KEYWORDS: Line edge roughness, Line width roughness, Lithography, Optical lithography, Semiconductor manufacturing, Chemical mechanical planarization, Dielectrophoresis

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Proceedings Article | 19 March 2015 Paper

Solving next generation (1x node) metrology challenges using advanced CDSEM capabilities: tilt, high energy and backscatter imaging

Xiaoxiao Zhang, Patrick Snow, Alok Vaid, Eric Solecky, Hua Zhou, Zhenhua Ge, Shay Yasharzade, Ori Shoval, Ofer Adan, Ishai Schwarzband, Maayan Bar-Zvi

Proceedings Volume 9424, 94240G (2015) https://doi.org/10.1117/12.2087267

KEYWORDS: Semiconducting wafers, 3D metrology, Overlay metrology, Metrology, Optical testing, Critical dimension metrology, Atomic force microscopy, Image segmentation, Scanning electron microscopy, Back end of line

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Traditional metrology solutions are facing a range of challenges at the 1X node such as three dimensional (3D) measurement capabilities, shrinking overlay and critical dimension (CD) error budgets driven by multi-patterning and via in trench CD measurements. Hybrid metrology offers promising new capabilities to address some of these challenges but it will take some time before fully realized. This paper explores new capabilities currently offered on the in-line Critical Dimension Scanning Electron Microscope (CD-SEM) to address these challenges and enable the CD-SEM to move beyond measuring bottom CD using top down imaging.

Device performance is strongly correlated with Fin geometry causing an urgent need for 3D measurements. New beam tilting capabilities enhance the ability to make 3D measurements in the front-end-of-line (FEOL) of the metal gate FinFET process in manufacturing. We explore these new capabilities for measuring Fin height and build upon the work communicated last year at SPIE¹. Furthermore, we extend the application of the tilt beam to the back-end-of-line (BEOL) trench depth measurement and demonstrate its capability in production targeting replacement of the existing Atomic Force Microscope (AFM) measurements by including the height measurement in the existing CDSEM recipe to reduce fab cycle time.

In the BEOL, another increasingly challenging measurement for the traditional CD-SEM is the bottom CD of the self-aligned via (SAV) in a trench first via last (TFVL) process. Due to the extremely high aspect ratio of the structure secondary electron (SE) collection from the via bottom is significantly reduced requiring the use of backscatter electrons (BSE) to increase the relevant image quality. Even with this solution, the resulting images are difficult to measure with advanced technology nodes. We explore new methods to increase measurement robustness and combine this with novel segmentation-based measurement algorithm generated specifically for BSE images. The results will be contrasted with data from previously used methods to quantify the improvement. We also compare the results to electrical test data to evaluate and quantify the measurement performance improvements.

Lastly, according to International Technology Roadmap for Semiconductors (ITRS) from 2013, the overlay 3 sigma requirement will be 3.3 nm in 2015 and 2.9 nm in 2016. Advanced lithography requires overlay measurement in die on features resembling the device geometry. However, current optical overlay measurement is performed in the scribe line on large targets due to optical diffraction limit. In some cases, this limits the usefulness of the measurement since it does not represent the true behavior of the device. We explore using high voltage imaging to help address this urgent need. Novel CD-SEM based overlay targets that optimize the restrictions of process geometry and SEM technique were designed and spread out across the die. Measurements are done on these new targets both after photolithography and etch. Correlation is drawn between the two measurements. These results will also be compared to conventional optical overlay measurement approaches and we will discuss the possibility of using this capability in high volume manufacturing.

SPIE Journal Paper | 1 October 2014

Addressing FinFET metrology challenges in 1× node using tilt-beam critical dimension scanning electron microscope

Xiaoxiao Zhang, Hua Zhou, Zhenhua Ge, Alok Vaid, Deepasree Konduparthi, Carmen Osorio, Stefano Ventola, Roi Meir, Ori Shoval, Roman Kris, Ofer Adan, Maayan Bar-Zvi

JM3, Vol. 13, Issue 04, 041407, (October 2014) https://doi.org/10.1117/12.10.1117/1.JMM.13.4.041407

KEYWORDS: Metrology, Transmission electron microscopy, Semiconducting wafers, Scanning electron microscopy, Electron microscopes, Process control, 3D metrology, Diffractive optical elements, Oxides

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Proceedings Article | 2 April 2014 Paper

Addressing FinFET metrology challenges in 1X node using tilt-beam CD-SEM

Xiaoxiao Zhang, Hua Zhou, Zhenhua Ge, Alok Vaid, Deepasree Konduparthi, Carmen Osorio, Stefano Ventola, Roi Meir, Ori Shoval, Roman Kris, Ofer Adan, Maayan Bar-Zvi

Proceedings Volume 9050, 90500C (2014) https://doi.org/10.1117/12.2046881

KEYWORDS: Transmission electron microscopy, Metrology, Semiconducting wafers, Process control, 3D metrology, Diffractive optical elements, Oxides, Calibration, Scanning electron microscopy

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