Self-aligned quadruple patterning (SAQP) has quickly become the most viable multi-patterning scheme adopted for manufacturing critical layers in logic and memory devices below the 10nm (N10) technology node. Occurrence of pitch walk is a very common phenomenon in post SAQP layers. If not properly managed, the absolute value and variability of pitch walk could result in either parametric yield degradation or catastrophic fin-loss defects. These issues result from the interaction with subsequent processes, such as keeps and cuts, which are used to define and isolate fin groups for building the transistors. Previous studies have shown that a combined lithography and etch methodology would help reduce the pitch walk impact . In this article, we will show advanced control for SAQP pitch walk using a combined scheme of lithography, deposition and etch actuators, in a front end 5nm logic process. By the implementation of a rigorous pitch walk prediction model that is calibrated and validated with wafer data, we then expand the model coverage to include an edge placement error component. This accounts for the contribution of overlay from subsequent layers to predict patterning defect probability at the final stage of device structure formation. With this approach, we can identify the optimal process control loop that minimizes pitch walk effects while maximizes the process margin for subsequent layers for this integration scheme.