Dr. Xuemei Chen Profile

Dr. Xuemei Chen

SPIE Involvement:

Editorial Board Member: Journal of Micro/Nanolithography, MEMS, and MOEMS | Editorial Board Member: Journal of Micro/Nanopatterning, Materials, and Metrology | Author

Area of Expertise:

EUV Lithography , Metrology Inspection , Process Modeling Control , Overlay , CDU , Predictive Analytics

Publications (18)

Proceedings Article | 24 March 2020 Presentation + Paper

Presentation + Paper

Advanced process control loop for SAQP pitch walk with combined lithography, deposition and etch actuators

Huan Ren, Antonio Mani, Sixiao Han, Xin Li, Xuemei Chen, Dieter Van Den Heuvel

Proceedings Volume 11325, 1132523 (2020) https://doi.org/10.1117/12.2552911

KEYWORDS: Etching, Semiconducting wafers, Lithography, Plasma etching, Critical dimension metrology, Process control, Actuators, Optical lithography, Scanning electron microscopy

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SPIE Journal Paper | 24 September 2018

Edge placement error fundamentals and impact of EUV: will traditional design-rule calculations work in the era of EUV?

Allen Gabor, Andrew Brendler, Timothy Brunner, Xuemei Chen, James Culp, Harry Levinson

JM3, Vol. 17, Issue 04, 041008, (September 2018) https://doi.org/10.1117/12.10.1117/1.JMM.17.4.041008

KEYWORDS: Critical dimension metrology, Extreme ultraviolet, Optical proximity correction, Semiconducting wafers, Line edge roughness, Stochastic processes, Extreme ultraviolet lithography, Cadmium, Semiconductors, Overlay metrology

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SPIE Journal Paper | 17 September 2018

Evaluation of EUV mask impacts on wafer line-width roughness using aerial and SEM image analyses

Xuemei Chen, Erik Verduijn, Obert Wood, Timothy A. Brunner, Renzo Capelli, Dirk Hellweg, Martin Dietzel, Grizelda Kersteen

JM3, Vol. 17, Issue 04, 041012, (September 2018) https://doi.org/10.1117/12.10.1117/1.JMM.17.4.041012

KEYWORDS: Line width roughness, Photomasks, Extreme ultraviolet, Semiconducting wafers, Scanning electron microscopy, Stochastic processes, Speckle, Scanners, Extreme ultraviolet lithography, Metrology

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Proceedings Article | 30 March 2018 Presentation + Paper

Presentation + Paper

EPE fundamentals and impact of EUV: Will traditional design-rule calculations work in the era of EUV?

Allen Gabor, Andrew Brendler, Timothy Brunner, Xuemei Chen, James Culp, Harry Levinson

Proceedings Volume 10583, 105830C (2018) https://doi.org/10.1117/12.2297459

KEYWORDS: Critical dimension metrology, Optical proximity correction, Semiconducting wafers, Line edge roughness, Extreme ultraviolet, Stochastic processes, Extreme ultraviolet lithography, Cadmium, Semiconductors, Overlay metrology

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The relationship between edge placement error, semiconductor design-rule determination and predicted yield in the era of EUV lithography is examined. This paper starts with the basics of edge placement error and then builds up to design-rule calculations. We show that edge placement error (EPE) definitions can be used as the building blocks for design-rule equations but that in the last several years the term “EPE” has been used in the literature to refer to many patterning errors that are not EPE. We then explore the concept of “Good Fields”¹ and use it predict the n-sigma value needed for design-rule determination. Specifically, fundamental yield calculations based on the failure opportunities per chip are used to determine at what n-sigma “value” design-rules need to be tested to ensure high yield. The “value” can be a space between two features, an intersect area between two features, a minimum area of a feature, etc. It is shown that across chip variation of design-rule important values needs to be tested at sigma values between seven and eight which is much higher than the four-sigma values traditionally used for design-rule determination. After recommending new statistics be used for design-rule calculations the paper examines the impact of EUV lithography on sources of variation important for design-rule calculations. We show that stochastics can be treated as an effective dose variation that is fully sampled across every chip. Combining the increased within chip variation from EUV with the understanding that across chip variation of design-rule important values needs to not cause a yield loss at significantly higher sigma values than have traditionally been looked at, the conclusion is reached that across-wafer, wafer-to-wafer and lot-to-lot variation will have to overscale for any technology introducing EUV lithography where stochastic noise is a significant fraction of the effective dose variation. We will emphasize stochastic effects on edge placement error distributions and appropriate design-rule setting. While CD distributions with long tails coming from stochastic effects do bring increased risk of failure (especially on chips that may have over a billion failure opportunities per layer) there are other sources of variation that have sharp cutoffs, i.e. have no tails. We will review these sources and show how distributions with different skew and kurtosis values combine.

Proceedings Article | 27 March 2018 Presentation + Paper

Presentation + Paper

Evaluation of EUV mask impacts on wafer line-edge roughness using aerial and SEM image analyses

Xuemei Chen, Erik Verduijn, Obert Wood, Timothy Brunner, Renzo Capelli, Dirk Hellweg, Martin Dietzel, Grizelda Kersteen

Proceedings Volume 10583, 105830J (2018) https://doi.org/10.1117/12.2297364

KEYWORDS: Line width roughness, Photomasks, Semiconducting wafers, Extreme ultraviolet, Scanning electron microscopy, Stochastic processes, Extreme ultraviolet lithography, Speckle, Image processing, Scanners

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Proceedings Article | 19 March 2018 Presentation + Paper

Presentation + Paper

Holistic analysis of aberration induced overlay error in EUV lithography

Yulu Chen, Lars Liebmann, Lei Sun, Allen Gabor, Shuo Zhao, Feixiang Luo, Obert Wood, Xuemei Chen, Daniel Schmidt, Michael Kling, Francis Goodwin

Proceedings Volume 10583, 105830D (2018) https://doi.org/10.1117/12.2297027

KEYWORDS: Aberration theory, Zernike polynomials, Diffraction, Extreme ultraviolet lithography, Wavefronts, Error analysis, Scanners, Photomasks, Overlay metrology, Lithography

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Proceedings Article | 16 October 2017 Presentation

Presentation

EUV mask flatness compensation strategies and requirements for reticle flatness, scanner optimization and E-beam writer (Conference Presentation)

Christina Turley, Jed Rankin, Xuemei Chen, Katherine Ballman, Christopher Lee, Tom Dunn

Proceedings Volume 10450, 104500A (2017) https://doi.org/10.1117/12.2280464

KEYWORDS: Reticles, Extreme ultraviolet, Scanners, Overlay metrology, Distortion, Manufacturing, Extreme ultraviolet lithography, Photomasks, High volume manufacturing, Lithography

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High volume manufacturing with extreme ultraviolet (EUV) lithography requires mask induced overlay errors of less than 1.5nm for the N7 node. The use of electrostatic chucking and reflective optics causes the reticle backside flatness and reticle thickness to directly affect the placement of the pattern at wafer through both in-plane (IPD) and out of plane distortions (OPD). The minimization of reticle flatness alleviates some of the image placement distortion caused by the reticle’s shape, however to be within the image placement error budget, N7 EUV blanks must have flatness <16nm p-v. With the manufacturing challenges associated with generating such flat blanks, compensation may be an option for imaging improvements; such methodologies will likely be essential for EUV to meet the stringent image placement and overlay specifications needed for high volume manufacturing (HVM). Numerous compensation approaches can be utilized to minimize flatness related image placement errors including write compensation of the reticle, feed forward of reticle flatness data to the scanner corrections, and high-order empirical scanner corrections. This study investigates the benefits and limitations of each of these approaches, and seeks to better define which types of errors can be compensated and which will need further reticle flatness development in order to meet N7 and N5 specifications. Additionally, attention is given to the reticle’s shape as it relates to the limitations to the depth of focus required within the scanner systems. Utilizing an array of substrates and blanks from different vendors, we provide an assessment on which type of compensation method is most effective for addressing the various topographies for each specific reticle, and further explore for which node such schemes may be necessary. This investigation seeks to provide a guide for the industry to work towards the implementation of functional tolerances related to both the compensation scheme used in manufacturing, and the reticle’s resulting non-correctable flatness (residual).

Proceedings Article | 28 March 2017 Presentation + Paper

Presentation + Paper

Level crossing methodology applied to line-edge roughness characterization

Chris Mack, Timothy Brunner, Xuemei Chen, Lei Sun

Proceedings Volume 10145, 101450Z (2017) https://doi.org/10.1117/12.2258602

KEYWORDS: Line scan image sensors, Line edge roughness, Statistical analysis, Image quality, Process control, Critical dimension metrology, Line width roughness, Extreme ultraviolet lithography, Correlation function, Computer simulations, Photoresist materials, Metrology, Edge roughness, Scanning electron microscopy, Edge detection, Lithography, Error analysis

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Proceedings Article | 24 March 2017 Presentation + Paper

Presentation + Paper

Minimizing wafer overlay errors due to EUV mask non-flatness and thickness variations for N7 production

Xuemei Chen, Christina Turley, Jed Rankin, Tim Brunner, Allen Gabor

Proceedings Volume 10143, 101431F (2017) https://doi.org/10.1117/12.2258642

KEYWORDS: Photomasks, Scanners, Semiconducting wafers, Extreme ultraviolet lithography, Error analysis, Lithographic illumination, Reticles, Overlay metrology, Distortion, Statistical analysis

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Proceedings Article | 24 March 2017 Presentation + Paper

Presentation + Paper

Line-edge roughness performance targets for EUV lithography

Timothy Brunner, Xuemei Chen, Allen Gabor, Craig Higgins, Lei Sun, Chris Mack

Proceedings Volume 10143, 101430E (2017) https://doi.org/10.1117/12.2258660

KEYWORDS: Line edge roughness, Extreme ultraviolet lithography, Extreme ultraviolet, Critical dimension metrology, Stochastic processes, Failure analysis, 193nm lithography, Photons, Logic, Modulation, Line width roughness, Photomasks, Cadmium, Statistical analysis, Image quality

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Proceedings Article | 24 March 2017 Presentation + Paper

Presentation + Paper

Mix-and-match considerations for EUV insertion in N7 HVM

Xuemei Chen, Allen Gabor, Pavan Samudrala, Sheldon Meyers, Erik Hosler, Richard Johnson, Nelson Felix

Proceedings Volume 10143, 101430F (2017) https://doi.org/10.1117/12.2258674

KEYWORDS: Extreme ultraviolet, Overlay metrology, Extreme ultraviolet lithography, Distortion, Control systems, Scanners, Imaging systems, Photomasks, Systems modeling, Error analysis, Semiconducting wafers, Reticles, Metrology

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Proceedings Article | 6 December 2004 Paper

Paper

Evaluation of printability of crystal growth defects in a 193-nm lithography environment using AIMS

Rainer Schmid, Axel Zibold, Kaustuve Bhattacharyya, Xuemei Chen, Brian Grenon

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569375

KEYWORDS: Lithography, Crystals, Reticles, Inspection, Photomasks, Printing, Semiconducting wafers, Scanners, Lithographic illumination, Raman spectroscopy

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Proceedings Article | 2 June 2003 Paper

Paper

Overlay excursion management through sample plan optimization and cycle time reduction

Xuemei Chen, Ming-Yeon Hung, Kelly Kuo, Steven Fu, Geoge Shanthikumar, Zhoujie Mao, Shiming Deng, Viral Hazari, Kevin Monahan, Mike Slessor, Amir Lev

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.485043

KEYWORDS: Semiconducting wafers, Overlay metrology, Metrology, Time metrology, Error analysis, Statistical analysis, Process control, Lithography, Yield improvement, Scanners

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Proceedings Article | 16 July 2002 Paper

Paper

Spectroscopic CD metrology for sub-100-nm lithography process control

Walter Mieher, Thaddeus Dziura, Xuemei Chen, Paola DeCecco, Ady Levy

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473424

KEYWORDS: Single crystal X-ray diffraction, Semiconducting wafers, Photoresist processing, Lithography, Critical dimension metrology, Process control, Metrology, Spectroscopy, Wafer testing, Reticles

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Proceedings Article | 16 July 2002 Paper

Paper

Microeconomics of advanced process window control for 50-nm gates

Kevin Monahan, Xuemei Chen, Georges Falessi, Craig Garvin, Matt Hankinson, Amir Lev, Ady Levy, Michael Slessor

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473503

KEYWORDS: Semiconducting wafers, Process control, Manufacturing, Information operations, Critical dimension metrology, Process modeling, Metrology, Etching, Lithography, Adaptive optics

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Proceedings Article | 16 July 2002 Paper

Paper

Advanced process control of overlay with optimal sampling

Craig Garvin, Xuemei Chen, Matt Hankinson

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473528

KEYWORDS: Overlay metrology, Process modeling, Process control, Metrology, Error analysis, Statistical modeling, Statistical analysis, Control systems, Device simulation, Semiconducting wafers

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Proceedings Article | 22 August 2001 Paper

Paper

Automated method for overlay sample plan optimization based on spatial variation modeling

Xuemei Chen, Moshe Preil, Mathilde Le Goff-Dussable, Mireille Maenhoudt

Proceedings Volume 4344, (2001) https://doi.org/10.1117/12.436749

KEYWORDS: Error analysis, Semiconducting wafers, Chemical mechanical planarization, Overlay metrology, Statistical analysis, Tolerancing, Oxides, Statistical modeling, Metals, Data modeling

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Proceedings Article | 14 June 1999 Paper

Paper

Measuring fab overlay programs

Richard Martin, Xuemei Chen, Itzik Goldberger

Proceedings Volume 3677, (1999) https://doi.org/10.1117/12.350871

KEYWORDS: Overlay metrology, Semiconducting wafers, Data modeling, Data analysis, Error analysis, Statistical analysis, Product engineering, Logic, Performance modeling, Semiconductors

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Showing 5 of 18 publications

Conference Committee Involvement (1)

Extreme Ultraviolet (EUV) Lithography X

25 February 2019 | San Jose, California, United States

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