A CMOS active pixel sensor array with anti-aliasing using distributed photodiodes that exhibit a 2-D sinc-like function has been fabricated and tested. Unlike the traditional rectilinear photodiode shapes, the sinc-function diode configurations are interleaved with neighboring pixels. This passive form of focal plane signal processing requires no additional circuitry or power, and depends only on the shape of each pixels sensor. Two such distributed sensor arrays were implemented on a single chip, one with pixels including first-order orthogonal side lobes, and one with first and second-order orthogonal side lobes as well as 1st-order diagonal side lobes. For comparisons, a conventional array with rectangular photodiodes was implemented on the same chip, with the same total sensor area as the second distributed version. Simulations of the filtering effectiveness of various pixel shapes will be presented, as well as measurements of pixel performance including leakage and noise. Of interest, distributed pixel sensors have a relatively larger periphery and hence higher capacitance, increased well-capacity and decreased charge-to-voltage gain relative to equal-area square sensors. The larger periphery raises a concern about increased leakage and noise. However, measurements showed less than 2% increase in leakage current and similarly small differences in noise.
A CMOS active pixel sensor array using column-level active reset has been fabricated and tested. Column-level active reset requires one additional transistor per pixel, bringing the total to 4, and a per-column op-amp. The added transistor per pixel controls the gate of the reset transistor. There are two important feedback mechanisms in active reset. The first is the amplification by the Miller effect of the effective capacitance on the photodiode during reset, hence reducing kT/C noise. The second is the control of the resetting current via modulation of the transconductance of the reset switch. The level of noise reduction is comparable to, or may exceed, what true correlated double sampling can achieve. Readout noise of 44 microvolts and a dynamic range of 90 dB (15 bits), rms, has been measured. Room temperature noise as low as 5.1 electrons, rms, referred back to the photodiode node, has been measured on small photodiode pixels (5.8 fF capacitance). This compares to 38.3 electrons when measured with a standard “hard” reset, for a factor of 7.6 improvement. Row and column fixed pattern noise were also improved by up to a factor of 21, going from 1% for both to 0.048% and 0.27%, respectively.
An image sensor acquisition and readout circuit prototype, capable of 4 to 10 million frames/s and 79 dB (13 bits), RMS, dynamic range has been fabricated and tested. The 0.35 μm CMOS chip tests sensor and readout circuitry intended for applications such as accelerator-based radiography, where fast, brief, transient events can be captured with high resolution. It exhibits a unique combination of extremely high speeds and very wide dynamic range, as well as 64-frame analog storage on the focal plane array (FPA). Each pixel includes either a charge-integrating trans-impedance amplifier or a direct-integration source-follower front end, followed by an array of 64 sample capacitors and associated readout electronics. Flexible operation capabilities allows the acquisition of either 32 frames using correlated double sampling (CDS) at 4 M-frames/s, or 64 frames without CDS at 7 M-frames/s without any reduction in gain. Allowing a -3dB gain reduction, frame rates as high as 10.5 MHz can be achieved. CDS is performed by acquiring two samples per frame, one immediately after reset and one at the end of the integration period, followed by external subtraction of the two samples. Two samples at a time are read out in parallel when CDS is not required. A 200 by 200 μm pixel is implemented in order to mate an extended version to an existing back-illuminated hybrid photo-diode FPA.