Sub-lithographic nanowires and nanogaps were fabricated by spacer lithography (size reduction technology), which is a parallel processes for nanometer pattern generation on a wafer scale with resolution comparable to the best electron beam lithography. Sub-10nm line width is defined by using a sacrificial ultrathin film deposited by low pressure chemical vapor deposition (LPCVD), in a process similar to formation of gate sidewall spacers in CMOS processing. Furthermore, a novel method called iterative spacer lithography
(ISL) is demonstrated by alternating materials and repeating the spacer lithography multiple times in order to multiply the pattern density. Silicon structures with sub-10nm width fabricated by this process were used as a mold in nanoimprint lithography and lift-off patterning of sub-30nm platinum nanowires for use as model catalyst systems. A similar process called reversed spacer lithography (RSL) is demonstrated to form sub-10nm nanogap device and fluid channels in poly-Si. This nanogap device provides a label-free tool for DNA
hybridization detection based on measuring capacitance changes in the gap.